2018

Carrillo-Nuñez, H., Mirza, M. M., Paul, D. J. , MacLaren, D. A. , Asenov, A. and Georgiev, V. P. (2018) Impact of randomly distributed dopants on Ω-gate junctionless silicon nanowire transistors. IEEE Transactions on Electron Devices, (doi:10.1109/TED.2018.2817919) (Early Online Publication)

2017

Mirza, M. M.A. , Schupp, F.J., Mol, J.A., MacLaren, D. , Briggs, G.A.D. and Paul, D. (2017) Many-Body Effects in 1D Degenerately-Doped Silicon Nanowire Devices. Silicon Quantum Information Processing (SiQIP), Lancaster, UK, 11 Sep 2017.

Radhakrishnan, N., Mirza, M. M.A. , MacLaren, D. and Paul, D. (2017) Electron Transport in Top-down Fabricated Silicon Nanowires Using Relaxed and Scalable Nanofabrication. Silicon Quantum Information Processing (SiQIP), Lancaster, UK, 11 Sep 2017.

Schupp, F. J., Mirza, M. M.A. , Mol, J.A., MacLaren, D. , Briggs, G.A.D. and Paul, D. (2017) Quantum Interference Effects in Degenerately Doped Silicon Nanowire Junction-less Transistors. Silicon Quantum Information Processing (SiQIP), Lancaster, UK, 11 Sep 2017.

Georgiev, V. P. , Mirza, M. M., Dochioiu, A.-I., Lema, F.-A., Amoroso, S. M., Towie, E., Riddet, C., MacLaren, D. A. , Asenov, A. and Paul, D. J. (2017) Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels. IEEE Transactions on Nanotechnology, 16(5), pp. 727-735. (doi:10.1109/TNANO.2017.2665691)

Zhou, H., Fu, Y.-C. and Mirza, M. (2017) Characterization of Al2O3 and HfO2 Grown on Metal Surfaces with Thermal and Plasma Enhanced Atomic Layer Deposition. AVS 17th International Conference on Atomic Layer Deposition (ALD 2017) featuring the 4th International Atomic Layer Etching Workshop (ALE 2017), Denver, CO, USA, 15-18 Jul 2017.

Mirza, M. M., Schupp, F. J., Mol, J. A., MacLaren, D. A. , Briggs, G. A. D. and Paul, D. J. (2017) One dimensional transport in silicon nanowire junction-less field effect transistors. Scientific Reports, 7, 3004. (doi:10.1038/s41598-017-03138-5) (PMID:28592820) (PMCID:PMC5462787)

Schupp, F., Mirza, M. M.A., MacLaren, D. , Briggs, A., Paul, D. and Mol, J. (2017) Silicon Transistors in Reduced Dimensions. American Physical Society (APS) March Meeting, New Orleans, LA, USA, 13-17 Mar 2017.

2016

Georgiev, V. P. , Mirza, M. M., Dochioiu, A.-I., Lema, F.-A., Amoroso, S. M., Towie, E., Riddet, C., MacLaren, D. A. , Asenov, A. and Paul, D. J. (2016) Experimental and Simulation Study of a High Current 1D Silicon Nanowire Transistor Using Heavily Doped Channels. In: 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), Toulouse, France, 9-12 Oct 2016, ISBN 9781509043521 (doi:10.1109/NMDC.2016.7777084)

Schupp, F. J., Mirza, M. M., MacLaren, D. A. , Briggs, A. A.D., Mol, J. A. and Paul, D. J. (2016) Top‐Down Fabricated Silicon Nanowire Junctionless Transistors. Silicon Quantum Electronics Workshop, Delft, Netherlands, 13-14 Jun 2016.

Paul, D., Mirza, M. M.A. and MacLaren, D. (2016) Si Nanowires and their Transistor Properties. EMN Meeting on Nanowires, Amsterdam, Netherlands, 16-19 May 2016.

2015

Schupp, F. et al. (2015) Ultra Scaled Silicon Nanowire Single Electron Transistors. Silicon Quantum Information Processing 2015: Scaling up (SiQIP2015), Cambridge, UK, 11 Sep 2015.

2014

Busche, C. et al. (2014) Design and fabrication of memory devices based on nanoscale polyoxometalate clusters. Nature, 515(7528), pp. 545-549. (doi:10.1038/nature13951) (PMID:25409147)

Mirza, M. M., MacLaren, D. A. , Samarelli, A., Holmes, B. M., Zhou, H., Thoms, S., MacIntyre, D. and Paul, D. J. (2014) Determining the electronic performance limitations in top-down fabricated Si nanowires with mean widths down to 4 nm. Nano Letters, 14(11), pp. 6056-6060. (doi:10.1021/nl5015298)

Samarelli, A., Mirza, M. M.A., Ferre Llin, L., MacLaren, D. and Paul, D. (2014) Lateral Transport and Thermoelectric Performance of Silicon Nanowires. In: 12th European Conference on Thermoelectrics, Madrid, Spain, 24–26 Sep 2014,

2013

Li, X., Ignatova, O., Cao, M., Peralagu, U. , Steer, M., Mirza, M., Zhou, H. and Thayne, I. (2013) 10 nm vertical In_0.53Ga_0.47As line etching process for III-V MOSFET fabrication by using inductively coupled plasma (ICP) etcher in C_l2/CH₄/H₂ chemistry. In: 26th International Microprocesses and Nanotechnology Conference (MNC), Royton Sapporo, Hokkaido, Japan, 5-8 Nov 2013,

Mirza, M. M., Thoms, S., Macintyre, D., MacLaren, D. and Paul, D. (2013) Fabrication and Characterization of Silicon Nanowires with Width Down to 1.9 nm. In: 39th International Conference on Micro and Nano Engineering (MNE), London, UK, 16-19 Sep 2013,

Samarelli, A., Ferre Llin, L., Mirza, M. M., MacLaren, D. and Paul, D. (2013) The Thermoelectric Properties of Sub-50 nm Silicon Nanowires. In: 39th International Conference on Micro and Nano Engineering (MNE), London, UK, 16-19 Sep 2013,

Mirza, M. M., MacLaren, D. and Paul, D. (2013) Silicon Nanowires with Widths Down to 1.9 nm for Breath Analysis Applications. Glasgow Research Partnership in Engineering (GRPE) Conference, Glasgow, UK, 19 Jun 2013.

Ignatova, O. et al. (2013) Towards vertical sidewalls in III-V FinFETs: dry etch processing and its associated damage on the electrical and physical properties of (100)-oriented InGaAs. In: 44th IEEE Semiconductor Interface Specialists Conference (SISC), Arlington, VA, USA, 5-7 Dec 2013, pp. 167-168.

2012

Mirza, M. M., Zhou, H., Velha, P., Li, X., Docherty, K. E., Samarelli, A., Ternent, G. and Paul, D. J. (2012) Nanofabrication of high aspect ratio (∼50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 30(6), 06FF02. (doi:10.1116/1.4755835)

Mirza, M. M. A., Zhou, H., Docherty, K., Thoms, S., Macintyre, D. and Paul, D. (2012) High Aspect Ratio (~25:1) Sub-10 Nm HSQ Lines Using Electron Beam Lithography. In: EIPBN 2012: The 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa,HI USA, 29 May - 01 June 2012., Waikoloa, HI, USA, 29 May - 1 June 2012,

Mirza, M.M., Velha, P., Ternent, G., Zhou, H.P., Docherty, K.E. and Paul, D.J. (2012) Silicon nanowire devices with widths below 5nm. In: 12th IEEE Conference on Nanotechnology, Birmingham, UK, 20-23 Aug 2012, (doi:10.1109/NANO.2012.6322005)

Mirza, M. M., Zhou, H., Velha, P., Li, X., Docherty, K. E., Samarelli, A., Ternent, G. and Paul, D. J. (2012) Nanofabrication of high aspect ratio (˜50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching. In: EIPBN 2012: The 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa,HI USA, 29 May - 01 June 2012,

Ternent, G., Mirza, M.M., Missous, M. and Paul, D. (2012) Scaling resonant tunnelling diodes and nanowires using SPICE modelling to optimise nanoscale performance. In: 12th IEEE Conference on Nanotechnology, Birmingham, UK, 20-23 Aug 2012, (doi:10.1109/NANO.2012.6322050)

Articles

Carrillo-Nuñez, H., Mirza, M. M., Paul, D. J. , MacLaren, D. A. , Asenov, A. and Georgiev, V. P. (2018) Impact of randomly distributed dopants on Ω-gate junctionless silicon nanowire transistors. IEEE Transactions on Electron Devices, (doi:10.1109/TED.2018.2817919) (Early Online Publication)

Georgiev, V. P. , Mirza, M. M., Dochioiu, A.-I., Lema, F.-A., Amoroso, S. M., Towie, E., Riddet, C., MacLaren, D. A. , Asenov, A. and Paul, D. J. (2017) Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels. IEEE Transactions on Nanotechnology, 16(5), pp. 727-735. (doi:10.1109/TNANO.2017.2665691)

Mirza, M. M., Schupp, F. J., Mol, J. A., MacLaren, D. A. , Briggs, G. A. D. and Paul, D. J. (2017) One dimensional transport in silicon nanowire junction-less field effect transistors. Scientific Reports, 7, 3004. (doi:10.1038/s41598-017-03138-5) (PMID:28592820) (PMCID:PMC5462787)

Busche, C. et al. (2014) Design and fabrication of memory devices based on nanoscale polyoxometalate clusters. Nature, 515(7528), pp. 545-549. (doi:10.1038/nature13951) (PMID:25409147)

Mirza, M. M., MacLaren, D. A. , Samarelli, A., Holmes, B. M., Zhou, H., Thoms, S., MacIntyre, D. and Paul, D. J. (2014) Determining the electronic performance limitations in top-down fabricated Si nanowires with mean widths down to 4 nm. Nano Letters, 14(11), pp. 6056-6060. (doi:10.1021/nl5015298)

Mirza, M. M., Zhou, H., Velha, P., Li, X., Docherty, K. E., Samarelli, A., Ternent, G. and Paul, D. J. (2012) Nanofabrication of high aspect ratio (∼50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 30(6), 06FF02. (doi:10.1116/1.4755835)

Conference or Workshop Item

Mirza, M. M.A. , Schupp, F.J., Mol, J.A., MacLaren, D. , Briggs, G.A.D. and Paul, D. (2017) Many-Body Effects in 1D Degenerately-Doped Silicon Nanowire Devices. Silicon Quantum Information Processing (SiQIP), Lancaster, UK, 11 Sep 2017.

Radhakrishnan, N., Mirza, M. M.A. , MacLaren, D. and Paul, D. (2017) Electron Transport in Top-down Fabricated Silicon Nanowires Using Relaxed and Scalable Nanofabrication. Silicon Quantum Information Processing (SiQIP), Lancaster, UK, 11 Sep 2017.

Schupp, F. J., Mirza, M. M.A. , Mol, J.A., MacLaren, D. , Briggs, G.A.D. and Paul, D. (2017) Quantum Interference Effects in Degenerately Doped Silicon Nanowire Junction-less Transistors. Silicon Quantum Information Processing (SiQIP), Lancaster, UK, 11 Sep 2017.

Zhou, H., Fu, Y.-C. and Mirza, M. (2017) Characterization of Al2O3 and HfO2 Grown on Metal Surfaces with Thermal and Plasma Enhanced Atomic Layer Deposition. AVS 17th International Conference on Atomic Layer Deposition (ALD 2017) featuring the 4th International Atomic Layer Etching Workshop (ALE 2017), Denver, CO, USA, 15-18 Jul 2017.

Schupp, F., Mirza, M. M.A., MacLaren, D. , Briggs, A., Paul, D. and Mol, J. (2017) Silicon Transistors in Reduced Dimensions. American Physical Society (APS) March Meeting, New Orleans, LA, USA, 13-17 Mar 2017.

Schupp, F. J., Mirza, M. M., MacLaren, D. A. , Briggs, A. A.D., Mol, J. A. and Paul, D. J. (2016) Top‐Down Fabricated Silicon Nanowire Junctionless Transistors. Silicon Quantum Electronics Workshop, Delft, Netherlands, 13-14 Jun 2016.

Paul, D., Mirza, M. M.A. and MacLaren, D. (2016) Si Nanowires and their Transistor Properties. EMN Meeting on Nanowires, Amsterdam, Netherlands, 16-19 May 2016.

Schupp, F. et al. (2015) Ultra Scaled Silicon Nanowire Single Electron Transistors. Silicon Quantum Information Processing 2015: Scaling up (SiQIP2015), Cambridge, UK, 11 Sep 2015.

Mirza, M. M., MacLaren, D. and Paul, D. (2013) Silicon Nanowires with Widths Down to 1.9 nm for Breath Analysis Applications. Glasgow Research Partnership in Engineering (GRPE) Conference, Glasgow, UK, 19 Jun 2013.

Conference Proceedings

Georgiev, V. P. , Mirza, M. M., Dochioiu, A.-I., Lema, F.-A., Amoroso, S. M., Towie, E., Riddet, C., MacLaren, D. A. , Asenov, A. and Paul, D. J. (2016) Experimental and Simulation Study of a High Current 1D Silicon Nanowire Transistor Using Heavily Doped Channels. In: 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), Toulouse, France, 9-12 Oct 2016, ISBN 9781509043521 (doi:10.1109/NMDC.2016.7777084)

Samarelli, A., Mirza, M. M.A., Ferre Llin, L., MacLaren, D. and Paul, D. (2014) Lateral Transport and Thermoelectric Performance of Silicon Nanowires. In: 12th European Conference on Thermoelectrics, Madrid, Spain, 24–26 Sep 2014,

Li, X., Ignatova, O., Cao, M., Peralagu, U. , Steer, M., Mirza, M., Zhou, H. and Thayne, I. (2013) 10 nm vertical In_0.53Ga_0.47As line etching process for III-V MOSFET fabrication by using inductively coupled plasma (ICP) etcher in C_l2/CH₄/H₂ chemistry. In: 26th International Microprocesses and Nanotechnology Conference (MNC), Royton Sapporo, Hokkaido, Japan, 5-8 Nov 2013,

Mirza, M. M., Thoms, S., Macintyre, D., MacLaren, D. and Paul, D. (2013) Fabrication and Characterization of Silicon Nanowires with Width Down to 1.9 nm. In: 39th International Conference on Micro and Nano Engineering (MNE), London, UK, 16-19 Sep 2013,

Samarelli, A., Ferre Llin, L., Mirza, M. M., MacLaren, D. and Paul, D. (2013) The Thermoelectric Properties of Sub-50 nm Silicon Nanowires. In: 39th International Conference on Micro and Nano Engineering (MNE), London, UK, 16-19 Sep 2013,

Ignatova, O. et al. (2013) Towards vertical sidewalls in III-V FinFETs: dry etch processing and its associated damage on the electrical and physical properties of (100)-oriented InGaAs. In: 44th IEEE Semiconductor Interface Specialists Conference (SISC), Arlington, VA, USA, 5-7 Dec 2013, pp. 167-168.

Mirza, M. M. A., Zhou, H., Docherty, K., Thoms, S., Macintyre, D. and Paul, D. (2012) High Aspect Ratio (~25:1) Sub-10 Nm HSQ Lines Using Electron Beam Lithography. In: EIPBN 2012: The 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa,HI USA, 29 May - 01 June 2012., Waikoloa, HI, USA, 29 May - 1 June 2012,

Mirza, M.M., Velha, P., Ternent, G., Zhou, H.P., Docherty, K.E. and Paul, D.J. (2012) Silicon nanowire devices with widths below 5nm. In: 12th IEEE Conference on Nanotechnology, Birmingham, UK, 20-23 Aug 2012, (doi:10.1109/NANO.2012.6322005)

Mirza, M. M., Zhou, H., Velha, P., Li, X., Docherty, K. E., Samarelli, A., Ternent, G. and Paul, D. J. (2012) Nanofabrication of high aspect ratio (˜50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching. In: EIPBN 2012: The 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa,HI USA, 29 May - 01 June 2012,

Ternent, G., Mirza, M.M., Missous, M. and Paul, D. (2012) Scaling resonant tunnelling diodes and nanowires using SPICE modelling to optimise nanoscale performance. In: 12th IEEE Conference on Nanotechnology, Birmingham, UK, 20-23 Aug 2012, (doi:10.1109/NANO.2012.6322050)