Dr Atif Jafri

  • Reader (Electronic & Nanoscale Engineering)

Biography

I did BSc in Electrical Engineering from UET Lahore, Pakistan in 1999. From 1999 to 2006 I served as Embedded System Designer in Advance Engineering and Research Organization (AERO), Pakistan.

In pursuit of higher education and excellence, I ventured to France from 2007 to 2011, where I earned my M.S. in Embedded Systems from the Université de Nice Sophia Antipolis and a Ph.D. on Unified Turbo Receivers from Université de Bretagne Sud. During my time in France, I remained engaged with Eurecom and Telecom Bretagne  where my research was focused on proposing flexible and high-throughput components for the physical layer of wireless communication systems.

Returning to Pakistan in 2011, I continued to contribute significantly, working as a Systems Engineer at AERO and concurrently serving as a visiting faculty member at Bahria University, Islamabad. In 2016, I became a full-time faculty member at Bahria University, dedicating my expertise to research areas such as hardware architectures for 5G communication waveforms, channel emulators, elliptic curve and ultra-lightweight cryptographic algorithms, and high-speed intrusion detection systems.

My leadership at the National Center for Cyber Security, where I led the hardware group in the Cyber Reconnaissance and Combat (CRC) Lab, highlights my commitment to cutting-edge research. My hands-on experience with Hardware Description Languages and realization of large-scale digital systems on FPGA further showcase my technical prowess.

From October 2023, I am part of Electronic & Nanoscale Engineering (ENE) Division of James Watt School of Engineering, University of Glasgow. 

Research interests

Hardware architecture for Qubit Control, signal processing implementation of waveforms and Intelligent Reflecting Surfaces (IRS) for 6G communication, high speed Intrusion Detection Systems (IDS) and Post Quantum Cryptography (PQC). 

Publications

List by: Type | Date

Jump to: 2022 | 2021 | 2020 | 2019
Number of items: 9.

2022

Umer, U., Rashid, M., Alharbi, A., Alhomoud, A., Kumar, H. and Jafri, A. R. (2022) An efficient crypto processor architecture for side-channel resistant Binary Huff Curves on FPGA. Electronics, 11(7), 1131. (doi: 10.3390/electronics11071131)

Najam-ul-Islam, M., Tu Zahra, F., Jafri, A. R. , Shah, R., ul Hassan, M. and Rashid, M. (2022) Auto implementation of parallel hardware architecture for Aho-Corasick algorithm. Design Automation for Embedded Systems, 26(1), pp. 29-53. (doi: 10.1007/s10617-021-09257-7)

2021

Khalid, M., Mujahid, U., Jafri, A. , Choi, H. and ul Islam Muhammad, N. (2021) An FPGA-based hardware abstraction of quantum computing systems. Journal of Computational Electronics, 20(5), pp. 2001-2018. (doi: 10.1007/s10825-021-01765-w)

Umaid Ali, S., Aamir, M., Jafri, A. R. , Subramaniam, U., Haroon, F., Waqar, A. and Yaseen, M. (2021) Model predictive control—based distributed control algorithm for bidirectional interlinking converter in hybrid microgrids. International Transactions on Electrical Energy Systems, 31(10), e12817. (doi: 10.1002/2050-7038.12817)

Imran, M., Bashir, F., Jafri, A. R. , Rashid, M. and Najam ul Islam, M. (2021) A systematic review of scalable hardware architectures for pattern matching in network security. Computers and Electrical Engineering, 92, 107169. (doi: 10.1016/j.compeleceng.2021.107169)

Sajid, A., Rashid, M., Imran, M. and Jafri, A. (2021) A low-complexity Edward-Curve point multiplication architecture. Electronics, 10(9), 1080. (doi: 10.3390/electronics10091080)

Najam-Ul-Islam, M., Nauman, M., Jafri, A. , Nadal, J., Abdel Nour, C. and Baghdadi, A. (2021) Hardware implementation of overlap-save-based fading channel emulator. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(3), pp. 918-922. (doi: 10.1109/tcsii.2020.3020724)

2020

Rashid, M., Imran, M., Jafri, A. R. and Mehmood, Z. (2020) A 4-stage pipelined architecture for point multiplication of binary huff curves. Journal of Circuits, Systems and Computers, 29(11), 2050179. (doi: 10.1142/s0218126620501790)

2019

Imran, M., Rashid, M., Jafri, A. R. and Kashif, M. (2019) Throughput/area optimised pipelined architecture for elliptic curve crypto processor. IET Computers and Digital Techniques, 13(5), pp. 361-368. (doi: 10.1049/iet-cdt.2018.5056)

This list was generated on Fri Apr 26 11:55:55 2024 BST.
Jump to: Articles
Number of items: 9.

Articles

Umer, U., Rashid, M., Alharbi, A., Alhomoud, A., Kumar, H. and Jafri, A. R. (2022) An efficient crypto processor architecture for side-channel resistant Binary Huff Curves on FPGA. Electronics, 11(7), 1131. (doi: 10.3390/electronics11071131)

Najam-ul-Islam, M., Tu Zahra, F., Jafri, A. R. , Shah, R., ul Hassan, M. and Rashid, M. (2022) Auto implementation of parallel hardware architecture for Aho-Corasick algorithm. Design Automation for Embedded Systems, 26(1), pp. 29-53. (doi: 10.1007/s10617-021-09257-7)

Khalid, M., Mujahid, U., Jafri, A. , Choi, H. and ul Islam Muhammad, N. (2021) An FPGA-based hardware abstraction of quantum computing systems. Journal of Computational Electronics, 20(5), pp. 2001-2018. (doi: 10.1007/s10825-021-01765-w)

Umaid Ali, S., Aamir, M., Jafri, A. R. , Subramaniam, U., Haroon, F., Waqar, A. and Yaseen, M. (2021) Model predictive control—based distributed control algorithm for bidirectional interlinking converter in hybrid microgrids. International Transactions on Electrical Energy Systems, 31(10), e12817. (doi: 10.1002/2050-7038.12817)

Imran, M., Bashir, F., Jafri, A. R. , Rashid, M. and Najam ul Islam, M. (2021) A systematic review of scalable hardware architectures for pattern matching in network security. Computers and Electrical Engineering, 92, 107169. (doi: 10.1016/j.compeleceng.2021.107169)

Sajid, A., Rashid, M., Imran, M. and Jafri, A. (2021) A low-complexity Edward-Curve point multiplication architecture. Electronics, 10(9), 1080. (doi: 10.3390/electronics10091080)

Najam-Ul-Islam, M., Nauman, M., Jafri, A. , Nadal, J., Abdel Nour, C. and Baghdadi, A. (2021) Hardware implementation of overlap-save-based fading channel emulator. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(3), pp. 918-922. (doi: 10.1109/tcsii.2020.3020724)

Rashid, M., Imran, M., Jafri, A. R. and Mehmood, Z. (2020) A 4-stage pipelined architecture for point multiplication of binary huff curves. Journal of Circuits, Systems and Computers, 29(11), 2050179. (doi: 10.1142/s0218126620501790)

Imran, M., Rashid, M., Jafri, A. R. and Kashif, M. (2019) Throughput/area optimised pipelined architecture for elliptic curve crypto processor. IET Computers and Digital Techniques, 13(5), pp. 361-368. (doi: 10.1049/iet-cdt.2018.5056)

This list was generated on Fri Apr 26 11:55:55 2024 BST.

Supervision

Teaching

Power Electronics


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