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Santra, T., Dixit, A., Jaisawal, R. K., Rathore, S., Sarkhel, S. and Bagga, N. (2022) Investigation of geometrical impact on a P+ buried negative capacitance SOI FET. Microelectronics Journal, 130, 105617. (doi: 10.1016/j.mejo.2022.105617)
Santra, T., Dixit, A., Jaisawal, R. K., Rathore, S., Sarkhel, S. and Bagga, N. (2022) Investigation of geometrical impact on a P+ buried negative capacitance SOI FET. Microelectronics Journal, 130, 105617. (doi: 10.1016/j.mejo.2022.105617)