Jude Haris
Research title: Designing Efficient Hardware Accelerators for Deep Neural Networks
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Research title: Designing Efficient Hardware Accelerators for Deep Neural Networks
Haris, J., Gibson, P. , Cano, J. , Bohm Agostini, N. and Kaeli, D. (2021) SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference. In: 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Belo Horizonte, Brazil, 26-28 Oct 2021, (In Press)
Haris, J. and Cano, J. (2020) Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs. 16th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Online, 06-17 Jul 2020.
Haris, J. and Cano, J. (2020) Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs. 16th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Online, 06-17 Jul 2020.
Haris, J., Gibson, P. , Cano, J. , Bohm Agostini, N. and Kaeli, D. (2021) SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference. In: 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Belo Horizonte, Brazil, 26-28 Oct 2021, (In Press)