Jude Haris
Research title: Hardware-Software Co-Design of FPGA-based Neural Network Accelerators for Edge Inference
Publications
2024
Agostini, N. B., Haris, J., Gibson, P. , Jayaweera, M., Rubin, N., Tumeo, A., Abellán, J. L., Cano Reyes, J. and Kaeli, D. (2024) AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators. In: International Symposium on Code Generation and Optimization (CGO) 2024, Edinburgh, United Kingdom, 02-06 Mar 2024, pp. 143-157. ISBN 9798350395099 (doi: 10.1109/CGO57630.2024.10444801)
2022
Haris, J., Gibson, P., Cano, J. , Agostini, N. B. and Kaeli, D. (2022) Hardware/Software Co-Design of Edge DNN Accelerators with TFLite. 18th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Fiuggi, Italy, 10-16 July 2022.
2021
Haris, J., Gibson, P. , Cano, J. , Bohm Agostini, N. and Kaeli, D. (2021) SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference. In: 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Belo Horizonte, Brazil, 26-28 Oct 2021, pp. 33-43. ISBN 9781665443012 (doi: 10.1109/SBAC-PAD53543.2021.00015)
2020
Haris, J. and Cano, J. (2020) Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs. 16th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Online, 06-17 Jul 2020.
Conference or Workshop Item
Haris, J., Gibson, P., Cano, J. , Agostini, N. B. and Kaeli, D. (2022) Hardware/Software Co-Design of Edge DNN Accelerators with TFLite. 18th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Fiuggi, Italy, 10-16 July 2022.
Haris, J. and Cano, J. (2020) Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs. 16th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Online, 06-17 Jul 2020.
Conference Proceedings
Agostini, N. B., Haris, J., Gibson, P. , Jayaweera, M., Rubin, N., Tumeo, A., Abellán, J. L., Cano Reyes, J. and Kaeli, D. (2024) AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators. In: International Symposium on Code Generation and Optimization (CGO) 2024, Edinburgh, United Kingdom, 02-06 Mar 2024, pp. 143-157. ISBN 9798350395099 (doi: 10.1109/CGO57630.2024.10444801)
Haris, J., Gibson, P. , Cano, J. , Bohm Agostini, N. and Kaeli, D. (2021) SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference. In: 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Belo Horizonte, Brazil, 26-28 Oct 2021, pp. 33-43. ISBN 9781665443012 (doi: 10.1109/SBAC-PAD53543.2021.00015)