Jude Haris

Research title: Designing and Generating Efficient FPGA-Based Accelerators for Deep Neural Networks

Publications

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Jump to: 2020
Number of items: 1.

2020

Haris, J. and Cano, J. (2020) Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs. 16th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Online, 06-17 Jul 2020.

This list was generated on Fri Jan 15 22:30:28 2021 GMT.
Number of items: 1.

Conference or Workshop Item

Haris, J. and Cano, J. (2020) Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs. 16th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Online, 06-17 Jul 2020.

This list was generated on Fri Jan 15 22:30:28 2021 GMT.