CAE & SoC Labs Workshop:
CMOS System-on-Chip Sandpit
Concept, Design, to Tape-Out
Together with SoC Labs, the CAE and EPSRC RaRE Network+ are delighted to host a sandpit workshop on CMOS ASIC design.
Anyone with an interest or experience in chip design is welcome to join this workshop. Find other collaborators for an opportunity to turn ideas into physical silicon chips, and develop your skills in IC design.
Workshop Topics:
- Intro to SoC Labs
- Good Dies example, available IP blocks and intro to FPGA prototyping
- IC block pitches: attendees can pitch their ideas for collaborations
- Group SoC Sandpit discuss with other attendees potential ASIC designs for SoC proposals.
Join us to partner with teams to pitch for potential tape-out projects. SoC Labs will run a call for ideas which will be supported to turn ideas to silicon, both financially and technically, in a range of processes, e.g. 65 nm, 14 nm.
AGENDA:
- 9.30, Arrival Coffee, Networking.
- 10.00 Introduction & SoC Labs intro
- Morning slot: intro to good dies
- 12:30 Lunch
- Afternoon slot: collaboration pitches
Date & Time:
4 December 2026, 9.30-4 pm. To be hosted at the University of Glasgow.