Atomistic Design of 2D InSe Semiconductor Transistors for Post-Silicon Technology
Supervisor: Prof Vihar Georgiev
School: Engineering
Description:
Silicon transistors are approaching fundamental physical limits. As devices are scaled to gate lengths below 10 nm, classical scaling strategies are no longer sufficient to sustain improvements in speed and energy efficiency. The semiconductor industry therefore faces a critical need for new channel materials and device architectures capable of delivering higher performance at lower operating voltages.
Two-dimensional (2D) layered semiconductors have attracted considerable attention as candidate channel materials for post-silicon electronics. Their atomically thin bodies provide inherently strong electrostatic gate control, suppressing the short-channel effects that degrade silicon device performance at nanometre scales. Among 2D semiconductors, indium selenide (InSe) is particularly promising: its low electron effective mass enables fast carrier transport, and its thin-body geometry allows aggressive device scaling while maintaining good electrostatic integrity.
Recent experimental work has demonstrated InSe transistors operating at 0.5 V with gate lengths of just 10 nm, achieving switching characteristics that surpass the best silicon devices reported to date. These results represent a significant milestone in the development of 2D semiconductor technology and suggest that InSe could play an important role in future integrated circuits. Nevertheless, a detailed physical understanding of the mechanisms governing carrier transport, contact behaviour, and electrostatic performance in these devices remains incomplete.
This project will address that gap through atomistic computer simulations of InSe transistors. Using the state-of-the-art quantum-mechanical modelling package QuantumATK, the student will investigate how device geometry, material composition, and contact design influence transistor performance at the nanometre scale. Simulations will be used to identify the physical factors that limit current device performance and to explore design strategies for further improvement.