Mr Jude Haris
- Research Associate (School of Computing Science)
Biography
Office: G132
School of Computing Science, Sir Alwyn Williams Building, 18 Lilybank Gardens, Glasgow G12 8RZ
Publications
2026
Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Amirafshar, Nima, Haris, Jude, TaheriNejad, Nima and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2026)
FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining.
In: 38th IEEE/SBC International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2026), Madrid, Spain, 14-16 Oct 2026,
(Accepted for Publication)
Dymarkowski, Hubert, Fu, Xingjian, Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Haris, Jude and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2026)
FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers.
In: 36th International Conference on Field-Programmable Logic and Applications (FPL 2026)., Ghent, Belgium, 7-11 September 2026,
(Accepted for Publication)
Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Haris, Jude, Bohm Agostini, Nicolas, Kaeli, David and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2026)
PoTAcc: a pipeline for end-to-end acceleration of power-of-two quantized DNNs.
IEEE Transactions on Circuits and Systems for Artificial Intelligence,
(doi: 10.1109/TCASAI.2026.3690415)
(Early Online Publication)
2025
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
Accelerating Transposed Convolutions on FPGA-based Edge Devices.
35th International Conference on Field-Programmable Logic and Applications (FPL) 2025, Leiden, The Netherlands, 1-5 Sept 2025.
(Accepted for Publication)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
SECDA Design Suite: Efficient Hardware-Software Co-Design of DNN Accelerator.
4th Workshop on Open-Source Computer Architecture Research (OSCAR) at ISCA 2025, Tokyo, Japan, 21 June 2025.
(Accepted for Publication)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs.
New Approaches for Addressing the Computing Requirements of LLMs and GNSs LG-ARC’2025 Workshop @ ISCA 2025, Tokyo, Japan, 22 June 2025.
(Accepted for Publication)
2024
Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Haris, Jude and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Accelerating PoT Quantization on Edge Devices.
In: 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18-20 Nov 2024,
ISBN 9798350377200
(doi: 10.1109/ICECS61496.2024.10849093)
Haris, Jude, Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Hu, Wenhao and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Designing Efficient LLM Accelerators for Edge Devices.
ARC-LG: New Approaches for Addressing the Computing Requirements of LLMs and GNNs, Buenos Aires, Argentina, 30 Jun 2024.
Haris, Jude, Agostini, Nicolas Bohm, Tumeo, Antonino, Kaeli, David and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR.
5th Compilers for Machine Learning Workshop (C4ML), at CGO 2024, Edinburgh, UK, 03 March 2024.
(doi: 10.48550/arXiv.2402.19184)
Agostini, Nicolas Bohm, Haris, Jude, Gibson, Perry ORCID: https://orcid.org/0000-0003-3370-0698, Jayaweera, Malith, Rubin, Norm, Tumeo, Antonio, Abellán, José L., Cano Reyes, Jose
ORCID: https://orcid.org/0000-0002-2243-389X and Kaeli, David
(2024)
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators.
In: International Symposium on Code Generation and Optimization (CGO) 2024, Edinburgh, United Kingdom, 02-06 Mar 2024,
pp. 143-157.
ISBN 9798350395099
(doi: 10.1109/CGO57630.2024.10444801)
2023
Haris, Jude, Gibson, Perry, Cano, José ORCID: https://orcid.org/0000-0002-2243-389X, Bohm Agostini, Nicolas and Kaeli, David
(2023)
SECDA-TFLite: a toolkit for efficient development of FPGA-based DNN accelerators for edge inference.
Journal of Parallel and Distributed Computing, 173,
pp. 140-151.
(doi: 10.1016/j.jpdc.2022.11.005)
2022
Haris, Jude, Gibson, Perry, Cano, José ORCID: https://orcid.org/0000-0002-2243-389X, Agostini, Nicolas Bohm and Kaeli, David
(2022)
Hardware/Software Co-Design of Edge DNN Accelerators with TFLite.
18th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Fiuggi, Italy, 10-16 July 2022.
2021
Haris, Jude, Gibson, Perry ORCID: https://orcid.org/0000-0003-3370-0698, Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X, Bohm Agostini, Nicolas and Kaeli, David
(2021)
SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference.
In: 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Belo Horizonte, Brazil, 26-28 Oct 2021,
pp. 33-43.
ISBN 9781665443012
(doi: 10.1109/SBAC-PAD53543.2021.00015)
2020
Haris, Jude and Cano, José ORCID: https://orcid.org/0000-0002-2243-389X
(2020)
Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs.
16th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Online, 06-17 Jul 2020.
Articles
Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Haris, Jude, Bohm Agostini, Nicolas, Kaeli, David and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2026)
PoTAcc: a pipeline for end-to-end acceleration of power-of-two quantized DNNs.
IEEE Transactions on Circuits and Systems for Artificial Intelligence,
(doi: 10.1109/TCASAI.2026.3690415)
(Early Online Publication)
Haris, Jude, Gibson, Perry, Cano, José ORCID: https://orcid.org/0000-0002-2243-389X, Bohm Agostini, Nicolas and Kaeli, David
(2023)
SECDA-TFLite: a toolkit for efficient development of FPGA-based DNN accelerators for edge inference.
Journal of Parallel and Distributed Computing, 173,
pp. 140-151.
(doi: 10.1016/j.jpdc.2022.11.005)
Conference or Workshop Item
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
Accelerating Transposed Convolutions on FPGA-based Edge Devices.
35th International Conference on Field-Programmable Logic and Applications (FPL) 2025, Leiden, The Netherlands, 1-5 Sept 2025.
(Accepted for Publication)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
SECDA Design Suite: Efficient Hardware-Software Co-Design of DNN Accelerator.
4th Workshop on Open-Source Computer Architecture Research (OSCAR) at ISCA 2025, Tokyo, Japan, 21 June 2025.
(Accepted for Publication)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs.
New Approaches for Addressing the Computing Requirements of LLMs and GNSs LG-ARC’2025 Workshop @ ISCA 2025, Tokyo, Japan, 22 June 2025.
(Accepted for Publication)
Haris, Jude, Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Hu, Wenhao and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Designing Efficient LLM Accelerators for Edge Devices.
ARC-LG: New Approaches for Addressing the Computing Requirements of LLMs and GNNs, Buenos Aires, Argentina, 30 Jun 2024.
Haris, Jude, Agostini, Nicolas Bohm, Tumeo, Antonino, Kaeli, David and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR.
5th Compilers for Machine Learning Workshop (C4ML), at CGO 2024, Edinburgh, UK, 03 March 2024.
(doi: 10.48550/arXiv.2402.19184)
Haris, Jude, Gibson, Perry, Cano, José ORCID: https://orcid.org/0000-0002-2243-389X, Agostini, Nicolas Bohm and Kaeli, David
(2022)
Hardware/Software Co-Design of Edge DNN Accelerators with TFLite.
18th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Fiuggi, Italy, 10-16 July 2022.
Haris, Jude and Cano, José ORCID: https://orcid.org/0000-0002-2243-389X
(2020)
Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs.
16th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Online, 06-17 Jul 2020.
Conference Proceedings
Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Amirafshar, Nima, Haris, Jude, TaheriNejad, Nima and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2026)
FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining.
In: 38th IEEE/SBC International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2026), Madrid, Spain, 14-16 Oct 2026,
(Accepted for Publication)
Dymarkowski, Hubert, Fu, Xingjian, Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Haris, Jude and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2026)
FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers.
In: 36th International Conference on Field-Programmable Logic and Applications (FPL 2026)., Ghent, Belgium, 7-11 September 2026,
(Accepted for Publication)
Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Haris, Jude and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Accelerating PoT Quantization on Edge Devices.
In: 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18-20 Nov 2024,
ISBN 9798350377200
(doi: 10.1109/ICECS61496.2024.10849093)
Agostini, Nicolas Bohm, Haris, Jude, Gibson, Perry ORCID: https://orcid.org/0000-0003-3370-0698, Jayaweera, Malith, Rubin, Norm, Tumeo, Antonio, Abellán, José L., Cano Reyes, Jose
ORCID: https://orcid.org/0000-0002-2243-389X and Kaeli, David
(2024)
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators.
In: International Symposium on Code Generation and Optimization (CGO) 2024, Edinburgh, United Kingdom, 02-06 Mar 2024,
pp. 143-157.
ISBN 9798350395099
(doi: 10.1109/CGO57630.2024.10444801)
Haris, Jude, Gibson, Perry ORCID: https://orcid.org/0000-0003-3370-0698, Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X, Bohm Agostini, Nicolas and Kaeli, David
(2021)
SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference.
In: 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Belo Horizonte, Brazil, 26-28 Oct 2021,
pp. 33-43.
ISBN 9781665443012
(doi: 10.1109/SBAC-PAD53543.2021.00015)