Mr Jude Haris
- Research Associate (School of Computing Science)
Biography
Office: G132
School of Computing Science, Sir Alwyn Williams Building, 18 Lilybank Gardens, Glasgow G12 8RZ
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Office: G132
School of Computing Science, Sir Alwyn Williams Building, 18 Lilybank Gardens, Glasgow G12 8RZ
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
Accelerating Transposed Convolutions on FPGA-based Edge Devices.
35th International Conference on Field-Programmable Logic and Applications (FPL) 2025, Leiden, The Netherlands, 1-5 Sept 2025.
(Accepted for Publication)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
SECDA Design Suite: Efficient Hardware-Software Co-Design of DNN Accelerator.
4th Workshop on Open-Source Computer Architecture Research (OSCAR) at ISCA 2025, Tokyo, Japan, 21 June 2025.
(Accepted for Publication)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs.
New Approaches for Addressing the Computing Requirements of LLMs and GNSs LG-ARC’2025 Workshop @ ISCA 2025, Tokyo, Japan, 22 June 2025.
(Accepted for Publication)
Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Haris, Jude and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Accelerating PoT Quantization on Edge Devices.
In: 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18-20 Nov 2024,
(Accepted for Publication)
Haris, Jude, Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Hu, Wenhao and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Designing Efficient LLM Accelerators for Edge Devices.
ARC-LG: New Approaches for Addressing the Computing Requirements of LLMs and GNNs, Buenos Aires, Argentina, 30 Jun 2024.
Haris, Jude, Agostini, Nicolas Bohm, Tumeo, Antonino, Kaeli, David and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR.
5th Compilers for Machine Learning Workshop (C4ML), at CGO 2024, Edinburgh, UK, 03 March 2024.
(doi: 10.48550/arXiv.2402.19184)
Haris, Jude, Gibson, Perry, Cano, José ORCID: https://orcid.org/0000-0002-2243-389X, Bohm Agostini, Nicolas and Kaeli, David
(2023)
SECDA-TFLite: a toolkit for efficient development of FPGA-based DNN accelerators for edge inference.
Journal of Parallel and Distributed Computing, 173,
pp. 140-151.
(doi: 10.1016/j.jpdc.2022.11.005)
Haris, Jude, Gibson, Perry, Cano, José ORCID: https://orcid.org/0000-0002-2243-389X, Bohm Agostini, Nicolas and Kaeli, David
(2023)
SECDA-TFLite: a toolkit for efficient development of FPGA-based DNN accelerators for edge inference.
Journal of Parallel and Distributed Computing, 173,
pp. 140-151.
(doi: 10.1016/j.jpdc.2022.11.005)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
Accelerating Transposed Convolutions on FPGA-based Edge Devices.
35th International Conference on Field-Programmable Logic and Applications (FPL) 2025, Leiden, The Netherlands, 1-5 Sept 2025.
(Accepted for Publication)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
SECDA Design Suite: Efficient Hardware-Software Co-Design of DNN Accelerator.
4th Workshop on Open-Source Computer Architecture Research (OSCAR) at ISCA 2025, Tokyo, Japan, 21 June 2025.
(Accepted for Publication)
Haris, Jude and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2025)
F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs.
New Approaches for Addressing the Computing Requirements of LLMs and GNSs LG-ARC’2025 Workshop @ ISCA 2025, Tokyo, Japan, 22 June 2025.
(Accepted for Publication)
Haris, Jude, Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Hu, Wenhao and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Designing Efficient LLM Accelerators for Edge Devices.
ARC-LG: New Approaches for Addressing the Computing Requirements of LLMs and GNNs, Buenos Aires, Argentina, 30 Jun 2024.
Haris, Jude, Agostini, Nicolas Bohm, Tumeo, Antonino, Kaeli, David and Cano, Jose ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR.
5th Compilers for Machine Learning Workshop (C4ML), at CGO 2024, Edinburgh, UK, 03 March 2024.
(doi: 10.48550/arXiv.2402.19184)
Saha, Rappy ORCID: https://orcid.org/0000-0001-9581-0193, Haris, Jude and Cano, José
ORCID: https://orcid.org/0000-0002-2243-389X
(2024)
Accelerating PoT Quantization on Edge Devices.
In: 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18-20 Nov 2024,
(Accepted for Publication)