View Specification DocumentFundamentals of Computer Systems UESTCHN5014
- Academic Session: 2026-27
- School: School of Engineering
- Credits: 20
- Level: Level 5 (SCQF level 11)
- Typically Offered: Semester 2
- Available to Visiting Students: No
- Collaborative Online International Learning: No
- Curriculum For Life: No
Short Description
Develop a deep understanding of the software-hardware interface and modern computer operation by designing and implementing a RISC-V processor emulator, thereby exposing computer architecture technical details, complexities, realities, and potential opportunities. Best software engineering practices are honed through the testing and verification integration to help ensure the implementation meets the engineering expectations as detailed in the RISC-V technical documentation. The course is preceded by, but a close companion to, Digital Design and Computer Organization, providing a complementary perspective of the software-hardware interface.
Timetable
The course will be delivered continuously in the traditional manner at UESTCHN.
Requirements of Entry
N/A
Excluded Courses
N/A
Co-requisites
N/A
Assessment
The final grade of the course consists of two portions: project score and final examination score. The final examination is given in an open-book and open-notes style. The lab assignments score is calculated as the sum of five, equally weighted written lab report assignments. The calculation of final grade is listed as below:
Lab assignments 25%
Final exam 75%
Main Assessment In: April/May
Course Aims
Effective embedded processor engineering requires systems-level programming experience and software-hardware interface knowledge. Furthermore, the rapid adoption of, e.g., the open hardware RISC-V platform, further blurs this interface, demanding a new generation of firmware engineers. The course exposes and illuminates this interface through the full emulation of a modern processor capable of running a suitably restricted version of the Linux operating system. Software engineering best practices are emphasized through utilization of revision control, continuous unit testing, and documentation.
Intended Learning Outcomes of Course
By the end of this course students will be able to:
1. Differentiate between data type encodings;
2. Compose assembly language programs using the RISC-V ISA;
3. Justify the modern computer architecture memory hierarchy, e.g., DRAM and cache;
4. Evaluate how closely the C memory model of stack and heap maps to the hardware model;
5. Design and implement a complex software system, i.e., the RISC-V emulator, to satisfy the given technical specifications;
6. Integrate software engineering best practices, e.g., revision control and continuous testing, into the software engineering development cycle.