Course Catalogue

Digital Design and Computer Organisation UESTCHN5009

  • Academic Session: 2026-27
  • School: School of Engineering
  • Credits: 20
  • Level: Level 5 (SCQF level 11)
  • Typically Offered: Semester 1
  • Available to Visiting Students: No
  • Collaborative Online International Learning: No
  • Curriculum For Life: No

Short Description

Computer architecture fundamentals are introduced from the foundation of simple digital logic components, to more complex, higher-level elements, and, finally, to a functional RISC-V processor simulated on an FPGA. Theoretical knowledge and trade-offs are reinforced through the practical design, simulation, and validation of high-level description language digital logic elements by utilizing continuous unit testing and formal verification techniques. The course is tightly integrated with Foundations of Computing Systems, approaching the software-hardware interface from the software to hardware perspective.

Timetable

The course will be delivered continuously in the traditional manner at UESTCHN.

Requirements of Entry

N/A

Excluded Courses

N/A

Co-requisites

N/A

Assessment

The final grade of the course consists of two portions: project score and final examination score. The final examination is given in an open-book and open-notes style. The project assignment will include a written, technical final report and a short (10 minute) oral presentation.

 

The calculation of final grade is listed as below:

Project score 50%

Final exam 50%

Main Assessment In: December

Course Aims

To learn computer architecture fundamentals from the hardware perspective, reinforcing that knowledge through the design, simulation, and validation of high-level design language of computer system elements. Students with knowledge and practical experience at the software-hardware interface fit a need in the growing embedded processors industry where technological developments, such as the rapid adoption of RISC-V, blur such boundaries. Formal verification and validation of complex systems are stressed throughout the course, instilling and developing software engineering best practices.

Intended Learning Outcomes of Course

By the end of this course students will be able to:

1. Distinguish and critique the primary elements of a contemporary, pipelined processor;

2. Analyse and design high-level design language (HDL) of digital logic and computer system elements;

3. Simulate and test HDL system components;

4. Develop debugging processes and techniques for FPGA systems;

5. Implement a continuous testing framework for validation and verification; and

6. Demonstrate a functional FPGA simulation of a RISC-V processor.

Minimum Requirement for Award of Credits

No exceptions