Application and Design of Digital Logic (UESTC) UESTCHN2001

  • Academic Session: 2023-24
  • School: School of Engineering
  • Credits: 16
  • Level: Level 2 (SCQF level 8)
  • Typically Offered: Semester 2
  • Available to Visiting Students: No

Short Description

This course introduces the design methods of digital circuits and system, leading from Logic Algebra, basic gates, functional modules to complex circuit (for example, CPU) based on FPGA chip. A range of examples are carried out in detail, as well as Hardware Description Language (HDL) and Electronic Design Automation (EDA) tools for Very Large-Scale Integrated Chip (VLSI) design.

Timetable

Course will be delivered continuously in the traditional manner at UESTC.

Requirements of Entry

Mandatory Entry Requirements

None

Recommended Entry Requirements

None

Excluded Courses

None

Co-requisites

None

Assessment

Assessment

75% Written Exam: closed-book final exam

5% Set Exercise: homework / tutorial exercises

20% Report: lab work / project work

Main Assessment In: April/May

Are reassessment opportunities available for all summative assessments? No

Due to the nature of the coursework, only the final exam can be reassessed.

The initial grade on Set Exercise (5%) and Report (20%) will be used when calculating the resit grade.

Course Aims

The aims of this course are to:

■ develop the skills in the design of simple digital circuits by manual,

■ develop the skills in the design of complex digital circuits by HDL and EDA tools,

■ provide a range of techniques in RISC CPU design, including the ISA, the datapath and the controller.

Intended Learning Outcomes of Course

By the end of this course students will be able to:

■ manipulate data in binary, octal and hexadecimal number representations,

■ design & analyse combinational circuits based on discrete gates, or on some common function modules (decoder, multiplexor, etc.),

■ design & analyse sequential circuits based on Flip/Flop, or on some common function modules (counter, shift register, etc.),

■ apply EDA tools and HDL language for VLSI (simple RISC CPU, etc.) design based on FPGA.

Minimum Requirement for Award of Credits

Students must submit at least 75% by weight of the components of the course's summative assessment. In addition, students must submit lab reports.