Course Catalogue

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Growth in the global microelectronics industry depends on the judicious packaging of electronic circuits, to both protect them from electrical and mechanical damage and to facilitate their integration into complex systems. This course describes the technologies behind current industrial microelectronic packaging approaches, including the properties of the physical materials typically used, and discusses how new packaging technologies can be developed.

Course will be delivered continuously in the traditional manner at UESTC.

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75% final Examination

25% Presentations based on individual and group research

Reassessments are normally available for all courses, except those which contribute to the Honours classification. For non-Honours courses, students are offered reassessment in all or any of the components of assessment if the satisfactory (threshold) grade for the overall course is not achieved at the first attempt. This is normally grade D3 for undergraduate students and grade C3 for postgraduate students. Exceptionally it may not be possible to offer reassessment of some coursework items, in which case the mark achieved at the first attempt will be counted towards the final course grade. Any such exceptions for this course are described below.

Due to the nature of the coursework and sequencing of courses, it is not possible to reassess the coursework project and laboratory.

The initial grade on coursework project and laboratory will be used when calculating the resit grade.

The aim of this course is to provide knowledge in aspects of the materials and processing techniques used in the modern microelectronics packaging industry, sufficient for future employment or research, to develop in students the skills to design microelectronics packaging based on industrially relevant criteria, and to give insight into current research in the field.

By the end of this course students will be able to:

■ assess the requirements of specific packaging (electrical, thermal and mechanical);

■ analyse qualitatively and quantitatively the effectiveness of packaging technologies;

■ summarize aspects of modern silicon die processing and die packaging associated with low- dielectrics, die thinning, and die interconnect;

■ evaluate the benefits and restrictions of modern system-on-package technologies (SOC/SIP/SOP/WLP).

Students must attend the degree examination and submit at least 75% by weight of the other components of the course's summative assessment.

Students should attend at least 75% of the timetabled classes of the course.

Note that these are minimum requirements: good students will achieve far higher participation/submission rates. Any student who misses an assessment or a significant number of classes because of illness or other good cause should report this by completing a MyCampus absence report.