Digital Circuit Design UESTC3020

  • Academic Session: 2019-20
  • School: School of Engineering
  • Credits: 20
  • Level: Level 3 (SCQF level 9)
  • Typically Offered: Semester 1
  • Available to Visiting Students: No
  • Available to Erasmus Students: No

Short Description

This course introduces the basics of digital electronics and Hardware Description Languages, developing the skills necessary to design complex digital systems that are made up from a mix of subsystems including state machines, counters, multi-function registers, memory and data processing units.

Timetable

This course will be timetabled in blocks, typically two weeks in four.

Requirements of Entry

Mandatory Entry Requirements

None

Recommended Entry Requirements

None

Excluded Courses

None

Co-requisites

None

Assessment

75% Examination

15% Laboratory report

10% Practical Skills Assessment

 

Students must submit work for assessment for the course laboratory or a grade of credit withheld will be given.

 

Reassessment

In accordance with the University's Code of Assessment reassessments are normally set for all courses which do not contribute to the honours classifications. For non honours courses, students are offered reassessment in all or any of the components of assessment if the satisfactory (threshold) grade for the overall course is not achieved at the first attempt. This is normally grade D3 for undergraduate students, and grade C3 for postgraduate students. Exceptionally it may not be possible to offer reassessment of some coursework items, in which case the mark achieved at the first attempt will be counted towards the final course grade. Any such exceptions are listed below in this box.

 

Due to the nature of the coursework and sequencing of courses, it is not possible to reassess the coursework laboratory.

Main Assessment In: April/May

Are reassessment opportunities available for all summative assessments? No

Reassessments are normally available for all courses, except those which contribute to the Honours classification. For non Honours courses, students are offered reassessment in all or any of the components of assessment if the satisfactory (threshold) grade for the overall course is not achieved at the first attempt. This is normally grade D3 for undergraduate students and grade C3 for postgraduate students. Exceptionally it may not be possible to offer reassessment of some coursework items, in which case the mark achieved at the first attempt will be counted towards the final course grade. Any such exceptions for this course are described below.

Due to the nature of the coursework and sequencing of courses, it is not possible to reassess the coursework laboratory.

 

The initial grade on coursework laboratories will be used when calculating the resit grade.

 

Reassessment is offered only to meet the special requirement that all courses must be passed for graduation in this programme.

Course Aims

The aim of this course is to provide a broad grounding in digital electronic systems, leading from basic gates to design at MSI and LSI functional block level aided by a hardware description language.

Intended Learning Outcomes of Course

By the end of this course students will be able to:

 

■ analyse fundamental (NAND, NOR, NOT) Boolean gates created from N and P-MOS transistors;

■ design, using manual methods, combinatorial logic functions and finite state machinges from simple Boolean gates;

■ describe how more complex logic circuits (including multiplexers, decoders and counters) may be constructed from simpler logic modules;

 

■ explain the principles of hierarchical design, design reuse, and design regularity, and demonstrate how these principles can be applied in practice using a hardware description language;

■ describe the process of logic synthesis;

■ list the key syntactic structures of VHDL;

■ design, using VHDL, key digital components such as: state machines, counters, multi-function registers, memory, and ALUs;

■ analyse the operation of given tranches of VHDL. Judge the quality of a given tranche of VHDL in producing efficient hardware;

 

■ list historical and present day types of programmable logic device including FPGAs.;

■ explain how hardware description languages can be used to program such devices;

■ design digital circuits at the level of the gate array field.;

■ evaluate the advantages and disadvantages of PLDs based on their underlying structures;

 

■ list the standard types of memory used in digital logic, identifying the advantages and disadvantages of each type, and their common commercial applications;

■ explain the physical operation of EEPROM memories;

■ analyse the operation of synchronous / collared RAM and calculate the maximum operating frequencies of such synchronous RAMs as a function of their internal structure;

■ design RAM modules with given size and timing, based on given memory subsystems;

 

■ state the key properties and practical uses of linear feedback shift registers;

■ identify the relationship between the structure of such a register and its characteristic polynomial;

■ calculate the order of a given linear feedback shift register, and be able to design one of maximal length;

 

■ describe the sources of metastability in digital logic and state the key structural aspects of common synchroniser designs;

■ calculate the mean time between failure of a given synchroniser, and design a synchroniser with a given mean time between failure given a series of design constraints;

■ assess the advantages and disadvantages of novel synchroniser designs against common design solutions;

■ design, in practice, VHLD systems with more than a single level of hierarchy, which incorporate the digital components mentioned above, to solve pre-defined problems.

Minimum Requirement for Award of Credits

Students must submit at least 75% by weight of the components (including examinations) of the course's summative assessment. In addition students must submit work for assessment for the course laboratory or a grade of credit withheld will be given.

 

Students must attend the timetabled laboratory classes.

 

Note that these are minimum requirements: good students will achieve far higher participation/submission rates. Any student who misses an assessment or a significant number of classes because of illness or other good cause should report this by completing a MyCampus absence report.