VLSI Design M ENG5092
- Academic Session: 2018-19
- School: School of Engineering
- Credits: 20
- Level: Level 5 (SCQF level 11)
- Typically Offered: Semester 1
- Available to Visiting Students: Yes
The course gives a broad coverage of the design of both digital and analogue very large scale integrated circuits, from the physical level through to the systems level, with an industrial context
2 x two hour session per week
Requirements of Entry
Mandatory Entry Requirements
Recommended Entry Requirements
70% Written Exam
30% Written Assignments
Main Assessment In: December
The aim of this course is to introduce both digital and analogue VLSI design, from the physical level through to the systems level.
Intended Learning Outcomes of Course
By the end of this course students will be able to:
■ explain the operation and the advantages of CMOS technology;
■ state Moore's Law and précis the effect of scaling rules on the operation of CMOS systems;
■ reproduce the cross section and layout of a CMOS inverter, and relate this information to CMOS layout design rules and design rules check (DRC) methods;
■ classify the simulation models used to describe the operation of CMOS devices, including at switch and gate levels;
■ summarise the industrial advantages of VLSI CMOS block based design (including the use of component design libraries / leaf cells);
Digital microelectronic circuits and subsystems
■ categorise different CMOS design styles (including And-Or-Invert, pass gate and dynamic logic) and critically evaluate their respective merits in an industrial context;
■ describe the architectures of latches, memory, shift registers, scan chains, and more complex subsystems such as mirror adders, Manchester carry adders and radix-2 array multipliers;
■ design adder and multiplier subsystems, making use of bit slicing and pipelining techniques;
■ select appropriate subsystems from commercial design libraries;
Analogue microelectronic circuits and subsystems
■ analyse and design simple CMOS analogue building blocks such as current mirrors, inverting amplifiers, source followers, cascaded circuits, and differential pair and gain stages;
■ analyse and design an industrially relevant two stage CMOS op-amp, with feedback, stability and compensation;
■ extract scalable device models from experimental characteristics, employ them in the design of analogue systems, and judge the benefits of such models;
■ evaluate the effects of transistor, capacitor and resistor layout on the performance of microelectronic circuits, particularly with respect to component matching;
Analogue-to-digital / Digital-to-Analogue conversion
■ compare and contrast the operation, advantages and limitations of a wide range of analogue to digital converters (including integrating, successive-approximation, algorithmic, flash, two-step, interpolating, folding, pipelined, and time-interleaved converters);
■ explain the benefits of oversampling converters, classify delta-sigma converters (first, second and higher order, bandpass and multi-bit), and design converters accounting for stability, idle tones and dithering;
■ analyse and contrast a wide range of industrially relevant digital to analogue converters (including resistor string, binary-scaled, R-2R, charge redistribution, thermometer-code and hybrid converters);
■ design analogue-to-digital and digital-to-analogue converters to a system specification;
■ break down a VSLI design problem into constituent tasks (including floor planning, layout, I/O and pad ring placement, power placements, logic place and route, clock place and route) and identify the appropriate CAD tools to facilitate each task;
■ evaluate the advantages of current industrial design flows / methodologies for ASIC design;
■ summarise the issues involved in functional and timing verification of VLSI systems and explain the various low level checks applied to a design before final fabrication.
Minimum Requirement for Award of Credits
Students must attend the degree examination and submit at least 75% by weight of the other components of the course's summative assessment.
Students must attend the timetabled laboratory classes.
Students should attend at least 75% of the timetabled classes of the course.
Note that these are minimum requirements: good students will achieve far higher participation/submission rates. Any student who misses an assessment or a significant number of classes because of illness or other good cause should report this by completing a MyCampus absence report.