VLSI Design 4 ENG4138

  • Academic Session: 2019-20
  • School: School of Engineering
  • Credits: 20
  • Level: Level 4 (SCQF level 10)
  • Typically Offered: Semester 1
  • Available to Visiting Students: Yes

Short Description

This course provides an introduction to both digital and analogue VLSI design, from the physical level through to the systems level.


2 x two hour sessions per week

Requirements of Entry

Mandatory Entry Requirements


Recommended Entry Requirements


Excluded Courses





90% Written Exam

10% Report

Main Assessment In: December

Are reassessment opportunities available for all summative assessments? Not applicable

Reassessments are normally available for all courses, except those which contribute to the Honours classification. For non Honours courses, students are offered reassessment in all or any of the components of assessment if the satisfactory (threshold) grade for the overall course is not achieved at the first attempt. This is normally grade D3 for undergraduate students and grade C3 for postgraduate students. Exceptionally it may not be possible to offer reassessment of some coursework items, in which case the mark achieved at the first attempt will be counted towards the final course grade. Any such exceptions for this course are described below. 

Course Aims

The aim of this course is to introduce both digital and analogue VLSI design, from the physical level through to the systems level.

Intended Learning Outcomes of Course

By the end of this course students will be able to:

Silicon technology

■ explain the operation and the advantages of CMOS technology;

■ state Moore's Law and prĂ©cis the effect of scaling rules on the operation of CMOS systems;

■ reproduce the cross section and layout of a CMOS inverter, and relate this information to CMOS layout design rules and design rules check (DRC) methods;

■ classify the simulation models used to describe the operation of CMOS devices, including at switch and gate levels;

■ summarise the advantages of VLSI CMOS block based design;

Digital microelectronic circuits and subsystems

■ categorise different CMOS design styles (including And-Or-Invert, pass gate and dynamic logic);

■ describe the architectures of latches, memory, shift registers, scan chains, and more complex subsystems such as mirror adders, Manchester carry adders and radix-2 array multipliers;

■ design adder and multiplier subsystems, making use of bit slicing and pipelining techniques;

■ select appropriate subsystems from available design libraries;

Analogue microelectronic circuits and subsystems

■ analyse and design simple CMOS analogue building blocks such as current mirrors, inverting amplifiers, source followers, cascoded circuits, and differential pair and gain stages;

■ analyse and design a two stage CMOS op-amp, with feedback, stability and compensation;

■ extract scalable device models from experimental characteristics, employ them in the design of analogue systems, and state why such models are important;

■ evaluate the effects of transistor, capacitor and resistor layout on the performance of microelectronic circuits, particularly with respect to component matching;

Analogue-to-digital / Digital-to-Analogue conversion

■ compare and contrast the operation, advantages and limitations of a wide range of analogue to digital converters (including integrating, successive-approximation, algorithmic, flash, two-step, interpolating, folding, pipelined, and time-interleaved converters);

■ explain the benefits of oversampling converters, classify delta-sigma converters (first, second and higher order, bandpass and multi-bit), and design converters accounting for stability, idle tones and dithering;

■ analyse and contrast the operation of common types of digital to analogue converters;

■ design analogue-to-digital and digital-to-analogue converters to a system specification;

VLSI Implementation

■ break down a VSLI design problem into constituent tasks (including floorplanning, layout, I/O and pad ring placement, power placements, logic place and route, clock place and route) and identify the appropriate CAD tools to facilitate each task;

■ give an overview of typical industry design flows/methodologies for ASIC design;

■ summarise the issues involved in functional and timing verification of VLSI systems and explain the various low level checks applied to a design before final fabrication.

Minimum Requirement for Award of Credits

Students must attend the degree examination and submit at least 75% by weight of the other components of the course's summative assessment.


Students must attend the timetabled laboratory classes.


Students should attend at least 75% of the timetabled classes of the course.


Note that these are minimum requirements: good students will achieve far higher participation/submission rates.  Any student who misses an assessment or a significant number of classes because of illness or other good cause should report this by completing a MyCampus absence report.