Digital Circuit Design 3 ENG3020

  • Academic Session: 2019-20
  • School: School of Engineering
  • Credits: 10
  • Level: Level 3 (SCQF level 9)
  • Typically Offered: Semester 2
  • Available to Visiting Students: Yes
  • Available to Erasmus Students: Yes

Short Description

Students who have already been introduced to the basics of digital electronics and Hardware Description Languages will develop, in Digital Circuit Design 3, the skills necessary to design complex digital systems which are made up from a mix of subsystems including: state machines, counters, multi-function registers, memory and data processing units.


2 lectures per week

Requirements of Entry

Mandatory Entry Requirements


Recommended Entry Requirements


Excluded Courses





90% Examination

10% Laboratory report

Main Assessment In: April/May

Course Aims

The aim of this course is to develop student's ability to design digital electronic systems at MSI and LSI functional block level.

Intended Learning Outcomes of Course

By the end of this course students will be able to:

■ explain the principles of hierarchical design, design reuse, and design regularity, and demonstrate how these principles can be applied in practice using a hardware description language;

■ describe the process of logic synthesis;

■ list the key syntactic structures of VHDL;

■ design, using VHDL, key digital components such as: state machines, counters, multi-function registers, memory, and ALUs;

■ design, using VHLD systems with more than a single level of hierarchy, which incorporate the digital components mentioned above, to solve pre-defined problems;

■ analyse the operation of given tranches of VHDL. Judge the quality of a given tranche of VHDL in producing efficient hardware;


■ list historical and present day types of programmable logic device including FPGAs.;

■ explain how hardware description languages can be used to program such devices;

■ design digital circuits at the level of the gate array field.;

■ evaluate the advantages and disadvantages of PLDs based on their underlying structures;


■ list the standard types of memory used in digital logic, identifying the advantages and disadvantages of each type, and their common commercial applications;

■ explain the physical operation of EEPROM memories;

■ analyse the operation of synchronous / collared RAM and calculate the maximum operating frequencies of such synchronous RAMs as a function of their internal structure;

■ design RAM modules with given size and timing, based on given memory subsystems;


■ state the key properties and practical uses of linear feedback shift registers;

■ identify the relationship between the structure of such a register and its characteristic polynomial;

■ calculate the order of a given linear feedback shift register, and be able to design one of maximal length;


■ describe the sources of metastability in digital logic and state the key structural aspects of common synchroniser designs;

■ calculate the mean time between failure of a given synchroniser, and design a synchroniser with a given mean time between failure given a series of design constraints;

■ assess the advantages and disadvantages of novel synchroniser designs against common design solutions.

Minimum Requirement for Award of Credits

Students must attend the degree examination and submit at least 75% by weight of the other components of the course's summative assessment.


Students must attend the timetabled laboratory classes.


Students should attend at least 75% of the timetabled classes of the course.


Note that these are minimum requirements: good students will achieve far higher participation/submission rates.  Any student who misses an assessment or a significant number of classes because of illness or other good cause should report this by completing a MyCampus absence report.