Towards the lower limit of Cryo-CMOS for scalability of Quantum Computer
Supervisor: Dr Fiheon Imroze
School: Engineering
Description:
In recent years, cryo-CMOS has gained tremendous attention from quantum computing hardware researchers for building control and read-out circuits for Qubits. Cryo-CMOS circuits have a significant role in the scalability of existing quantum computers. Typically, superconducting qubits operate at the millikelvin temperature stage while the control and read-out circuit is placed at much higher temperatures, such as the 4K stage or 77K stage, depending upon the reliable PDK availability that is still at the research and development phase. The millikelvin temperature stage has a thermal budget, i.e., the power dissipation can’t exceed 500µW to be maintained at 100 mK while its 12µW to be maintained at 20 mK. Ideally, there should be zero power dissipation to reach the base temperature, i.e., 10mK. In this regard, there are efforts in the Qubit design to raise the operating range and lower the power dissipation by the cryo-CMOS circuit.
In this project, we propose to simulate a bulk CMOS/FDSOI device in Sentaurus TCAD at the lowest temperature possible such that the power dissipation is the lowest. The aim is to determine the lower limit of the power dissipation in the cryo-CMOS circuits, which is a necessary step toward scalability. Currently, we don’t have reliable PDKs for the bulk CMOS/FDSOI transistors. In such a scenario, control and read-out circuit simulation is not possible. However, in TCAD, it is possible to converge device simulation at cryogenic temperatures. There can be several approaches in TCAD to implement this, i.e., choosing an appropriate transport model that can accommodate the cryogenic temperature effects in the device, tuning the mobility model parameters, or using the Monte Carlo simulation approach available in TCAD. The simulation data will be compared to experimental data available at 77K and 4K in the initial phase for a sanity check. Once the simulation is optimized, the device will be simulated at further low temperatures to achieve the lowest power dissipation limit. The power dissipation in the control and read-out circuit will be predicted based on the power dissipation of the individual transistors simulated at the desired operating point for the circuit. The lower limit of the power dissipation in the cryo-CMOS circuit can thus be predicted, which allows us to decide the appropriate lowest temperature stage for the control and read-out circuit.