#### revooridinesh

##### Member level 1

**could some one convert this non synthesizable VHDL code to synthesizable**

hi

i am new to VHDL

i have written a code to convert real values to 3 bit but real values cannot be synthesizable so is there any way to convert below non-synthesizable to synthesizable ?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity fpadc is

port (clk :in std_logic;

bit2,bit1,bit0: out bit);

end fpadc;

architecture Behavioral of fpadc is

type sinvalues is array (0 to 12) of real;

signal sine : sinvalues :=(16.21,31.04,45.54,58.24,67.2,74.12,77.32,77.44,74.24,67.02,58.48,45.36,31.12,16.45);

signal inst : real;

begin

process(clk)

variable i : integer := 0;

--variable mn : real := 0.00;

--signal i : integer range 0 to 30:=0;

begin

if(rising_edge(clk)) then

inst <= sine(i);

i :=i+1;

--mn := 0.00-inst;

if ((inst<0.10 and inst>=0.00 ) or (inst>-0.10 and inst<=0.00) ) then --or

bit2<='0';

bit1<='0';

bit0<='0';

elsif ((inst<1.00 and inst>=0.10 )or (inst>-1.00 and inst<=-0.10) ) then --

bit2<='0';

bit1<='0';

bit0<='1';

elsif ((inst<10.00 and inst>=1.00 )or (inst>10.00 and inst<=-1.00)) then --

bit2<='0';

bit1<='1';

bit0<='0';

elsif ((inst<100.00 and inst>=10.00 ) or (inst>-100.00 and inst<=-10.00)) then --

bit2<='0';

bit1<='1';

bit0<='1';

elsif ((inst<1000.00 and inst>=100.00 ) or (inst>-1000.00 and inst<=-100.00)) then --

bit2<='1';

bit1<='0';

bit0<='0';

end if;

if(i = 12) then

i := 0;

end if;

end if;

end process;

end Behavioral;

Thank You

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