Computer Architecture (H) COMPSCI4007
- Academic Session: 2023-24
- School: School of Computing Science
- Credits: 10
- Level: Level 4 (SCQF level 10)
- Typically Offered: Semester 1
- Available to Visiting Students: Yes
The course explains in depth how a computer works, by developing a digital circuit that implements an instruction set architecture. Topics include cache, virtual memory, support by the architecture for the operating system, and instruction level parallelism.
3 hours per week
Examination 80%, coursework 20%.
Main Assessment In: April/May
Are reassessment opportunities available for all summative assessments? No
Reassessments are normally available for all courses, except those which contribute to the Honours classification. For non Honours courses, students are offered reassessment in all or any of the components of assessment if the satisfactory (threshold) grade for the overall course is not achieved at the first attempt. This is normally grade D3 for undergraduate students and grade C3 for postgraduate students. Exceptionally it may not be possible to offer reassessment of some coursework items, in which case the mark achieved at the first attempt will be counted towards the final course grade. Any such exceptions for this course are described below.
Resit examinations ARE NOT ALLOWED for Honours students.
Resit examinations ARE ALLOWED for Masters students.
The coursework cannot be redone because the feedback provided to the students after the original coursework would give any student redoing the coursework an unfair advantage. The nature of the coursework is such that it takes a significant number of days to produce it and this effort is infeasible for supporting the re-doing of such coursework over the summer.
This course provides a working understanding of the fundamental principles of computer systems. It answers the question "How do computers work?" at a substantive level, as well as giving a foundation needed for other areas in computer systems. The course reviews the behaviour of digital circuits and introduces a functional hardware description language for specifying and simulating synchronous circuits. Using the hardware description language, a complete and precise design of a simple but realistic computer architecture is developed. Advanced topics include the memory system, pipelining, superscalar organisation, and interaction between the architecture and operating system, and the use of formal methods in hardware design. Current trends are introduced, in particular parallelism and reconfigurable computing.
Intended Learning Outcomes of Course
By the end of the course students will be able to:
1. Demonstrate understanding of a processor datapath design, and be able to derive the control signal settings required to make the datapath perform an operation;
2. Implement the datapath and the control as digital circuits;
3. Use simulation to explore properties of a processor circuit;
4. Analyse the behaviour of a processor pipeline as the processor executes various sequences of instructions;
5. Predict the impact of the memory hierarchy on system performance;
6. Describe how the operating system utilizes the architecture's support in order to provide processes, protection, virtual memory, and input/output;
7. Discuss the role of parallelism in current and future architectures.
Minimum Requirement for Award of Credits
Students must submit at least 75% by weight of the components (including examinations) of the course's summative assessment.