Mr Mahesh Soni
- Research Assistant (Electronic & Nanoscale Engineering)
I am an Electronics Engineer and my research interest includes areas such as Semiconductor Device Fabrication, Device Physics, 2D Materials based Electronic and Non-Volatile Memory devices (FLASH, Memristors), Printable and Flexible Electronics, Conductive Inks for Interconnects, Smart Lithography and Sensors.
Research - Social Media
Overview - Brief Bio
Mahesh is currently a Post Doctoral Research Assistant (PDAR) (Since December 2018) in Bendable Electronics and Sensing Technologies (BEST) group, Electronics and Nanoengineering at the University of Glasgow, Scotland (United Kingdom). He is working on the integration of flexible one transistor - one memory (1T - 1M) structures for electronic skin (e-Skin) and tactile neuromorphic applications.
Before joining the University of Glasgow, he completed his Doctor of Philosophy (Ph.D.) (Feb 2014 - Nov 2018) at Indian Institute of Technology Mandi (Himachal Pradesh), India with Dr. Satinder Kumar Sharma and Dr. Ajay Soni in School of Computing and Electrical Engineering. His Ph.D. thesis work is based on "Graphene and Derivatives Based Scaled Electronic and Memory Devices for Next Generation Technology”. He has more than 5 years of hands-on experience in the clean room and semiconductor device fabrication facilities at:-
- James Watt Nanofabrication Centre, University of Glasgow (Scotland), United Kingdom
- Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science Bengaluru (Karnataka), India
- Centre of Excellence in Nanoelectronics (CEN), Indian Institute of Technology Bombay (Maharashtra), India
- Centre for Desing and Fabrication of Electronic Devices (C4DFED), Indian Institute of Technology Mandi (Himachal Pradesh), India
He was working as an Assitant professor in the Department of Electronics and Communication Engineering at GLA University Mathura (Uttar Pradesh), India (July 2012 - Feb 2014). During his tenure at GLA University, his major job was Teaching, training young minds and to carry out research activities.
He obtained his degree in Masters of Technology (M.Tech) (August 2010 - 2012) in the Department of Electronics and Communication Engineering at Malaviya National Institute of Technology Jaipur (Rajasthan), India with specialization in VLSI Design. For his M.Tech project, he was working with Prof. Vineet Shula and his M.Tech dissertation title was "Exploration of Power Optimal High Performance Multi Valued Circuits using Carbon Nanotube based FET (CNFET)". For his M.Tech, he carried out simulations in the HSPICE tool. Apart from the major project, he also completed a minor project entitled "180 nm Implementation of Accurate, Efficient FFT Algorithm", where he performed simulations in MATLAB and HSPICE. For getting selected for his M.Tech, he cleared the national level eligibility test "GATE" (Graduate Aptitude test in ENgineering) in the year 2010, with 95 percentile.