Mr Jaehyun Lee

  • Research Associate (Electronic and Nanoscale Engineering)

Publications

List by: Type | Date

Jump to: 2017 | 2014
Number of items: 6.

2017

Thirunavukkarasu, V. et al. (2017) Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs. Superlattices and Microstructures, (doi:10.1016/j.spmi.2017.07.020) (In Press)

Lee, J., Kim, S. and Shin, M. (2017) A theoretical model for predicting Schottky-barrier height of the nanostructured silicide-silicon junction. Applied Physics Letters, 110(23), 233110. (doi:10.1063/1.4985013)

Lee, J. et al. (2017) Atoms-to-Circuits Simulation Investigation of CNT Interconnects for Next Generation CMOS Technology. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, (Accepted for Publication)

Lee, J. et al. (2017) The Impact of Vacancy Defects on CNT Interconnects: From Statistical Atomistic Study to Circuit Simulations. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, (Accepted for Publication)

Lee, J., Sadi, T., Georgiev, V. P. , Todri-Sanial, A. and Asenov, A. (2017) A Hierarchical Model for CNT and Cu-CNT Composite Interconnects: From Density Functional Theory to Circuit-Level Simulations. International Workshop on Computational Nanotechnology, Windermere, UK, 5-9 June 2017. (Unpublished)

2014

Seo, J., Lee, J. and Shin, M. (2014) Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications. IEEE Transactions on Electron Devices, 64(4), pp. 1793-1798. (doi:10.1109/TED.2017.2658673)

This list was generated on Tue Oct 17 17:58:09 2017 BST.
Number of items: 6.

Articles

Thirunavukkarasu, V. et al. (2017) Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs. Superlattices and Microstructures, (doi:10.1016/j.spmi.2017.07.020) (In Press)

Lee, J., Kim, S. and Shin, M. (2017) A theoretical model for predicting Schottky-barrier height of the nanostructured silicide-silicon junction. Applied Physics Letters, 110(23), 233110. (doi:10.1063/1.4985013)

Seo, J., Lee, J. and Shin, M. (2014) Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications. IEEE Transactions on Electron Devices, 64(4), pp. 1793-1798. (doi:10.1109/TED.2017.2658673)

Conference or Workshop Item

Lee, J., Sadi, T., Georgiev, V. P. , Todri-Sanial, A. and Asenov, A. (2017) A Hierarchical Model for CNT and Cu-CNT Composite Interconnects: From Density Functional Theory to Circuit-Level Simulations. International Workshop on Computational Nanotechnology, Windermere, UK, 5-9 June 2017. (Unpublished)

Conference Proceedings

Lee, J. et al. (2017) Atoms-to-Circuits Simulation Investigation of CNT Interconnects for Next Generation CMOS Technology. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, (Accepted for Publication)

Lee, J. et al. (2017) The Impact of Vacancy Defects on CNT Interconnects: From Statistical Atomistic Study to Circuit Simulations. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, (Accepted for Publication)

This list was generated on Tue Oct 17 17:58:09 2017 BST.