Mr Jaehyun Lee

  • Research Associate (Electronic and Nanoscale Engineering)

Publications

List by: Type | Date

Jump to: 2018 | 2017 | 2014
Number of items: 13.

2018

Carrillo-Nunez, H., Lee, J., Berrada, S., Medina-Bailon, C., Adamu-Lema, F., Luisier, M., Asenov, A. and Georgiev, V. P. (2018) Random dopant-induced variability in Si-InAs nanowire tunnel FETs: a quantum transport simulation study. IEEE Electron Device Letters, (doi:10.1109/LED.2018.2859586) (Early Online Publication)

Lee, J. et al. (2018) Understanding electromigration in Cu-CNT composite interconnects: a multiscale electrothermal simulation study. IEEE Transactions on Electron Devices, (doi:10.1109/TED.2018.2853550) (Early Online Publication)

Liang, J., Lee, J., Berrada, S., Georgiev, V. , Pandey, R. R., Chen, R., Asenov, A. and Todri-Sanial, A. (2018) Atomistic to circuit-level modeling of doped SWCNT for on-chip interconnects. IEEE Transactions on Nanotechnology, (doi:10.1109/TNANO.2018.2802320) (Early Online Publication)

2017

Thirunavukkarasu, V. et al. (2017) Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs. Superlattices and Microstructures, 111, pp. 649-655. (doi:10.1016/j.spmi.2017.07.020)

Lee, J. et al. (2017) The Impact of Vacancy Defects on CNT Interconnects: From Statistical Atomistic Study to Circuit Simulations. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, pp. 157-160. (doi:10.23919/SISPAD.2017.8085288)

Lee, J. et al. (2017) Atoms-to-Circuits Simulation Investigation of CNT Interconnects for Next Generation CMOS Technology. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, pp. 153-156. (doi:10.23919/SISPAD.2017.8085287)

Berrada, S., Lee, J., Georgiev, V. and Asenov, A. (2017) Effect of the Quantum Mechanical Tunneling on the Leakage Current in Ultra-scaled Si Nanowire Transistors. 12th IEEE Nanotechnology Materials and Devices Conference (NMDC 2017), Singapore, 2-4 Oct 2017. (Accepted for Publication)

Liang, J., Lee, J., Berrada, S., Georgiev, V. , Asenov, A., Azemard-Crestani, A. and Todri-Sanial, A. (2017) Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application. In: 12th IEEE Nanotechnology Materials and Devices Conference (NMDC 2017), Singapore, 2-4 Oct 2017, (Accepted for Publication)

Lee, J., Kim, S. and Shin, M. (2017) A theoretical model for predicting Schottky-barrier height of the nanostructured silicide-silicon junction. Applied Physics Letters, 110(23), 233110. (doi:10.1063/1.4985013)

Lee, J., Sadi, T., Georgiev, V. P. , Todri-Sanial, A. and Asenov, A. (2017) A Hierarchical Model for CNT and Cu-CNT Composite Interconnects: From Density Functional Theory to Circuit-Level Simulations. International Workshop on Computational Nanotechnology, Windermere, UK, 5-9 June 2017. (Unpublished)

Adamu-Lema, F., Duan, M. , Berrada, S., Lee, J., Al-Ameri, T. , Georgiev, V. and Asenov, A. (2017) Modelling and simulation of advanced semiconductor devices. ECS Transactions, 80(4), pp. 33-42. (doi:10.1149/08004.0033ecst)

Liang, J. et al. (2017) A Physics-based Investigation of Pt-salt Doped Carbon Nanotubes for Local Interconnects. In: 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 02-06 Dec 2017, 35.5.1-35.5.4. ISBN 9781538635599 (doi:10.1109/IEDM.2017.8268502)

2014

Seo, J., Lee, J. and Shin, M. (2014) Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications. IEEE Transactions on Electron Devices, 64(4), pp. 1793-1798. (doi:10.1109/TED.2017.2658673)

This list was generated on Tue Aug 14 16:58:49 2018 BST.
Number of items: 13.

Articles

Carrillo-Nunez, H., Lee, J., Berrada, S., Medina-Bailon, C., Adamu-Lema, F., Luisier, M., Asenov, A. and Georgiev, V. P. (2018) Random dopant-induced variability in Si-InAs nanowire tunnel FETs: a quantum transport simulation study. IEEE Electron Device Letters, (doi:10.1109/LED.2018.2859586) (Early Online Publication)

Lee, J. et al. (2018) Understanding electromigration in Cu-CNT composite interconnects: a multiscale electrothermal simulation study. IEEE Transactions on Electron Devices, (doi:10.1109/TED.2018.2853550) (Early Online Publication)

Liang, J., Lee, J., Berrada, S., Georgiev, V. , Pandey, R. R., Chen, R., Asenov, A. and Todri-Sanial, A. (2018) Atomistic to circuit-level modeling of doped SWCNT for on-chip interconnects. IEEE Transactions on Nanotechnology, (doi:10.1109/TNANO.2018.2802320) (Early Online Publication)

Thirunavukkarasu, V. et al. (2017) Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs. Superlattices and Microstructures, 111, pp. 649-655. (doi:10.1016/j.spmi.2017.07.020)

Lee, J., Kim, S. and Shin, M. (2017) A theoretical model for predicting Schottky-barrier height of the nanostructured silicide-silicon junction. Applied Physics Letters, 110(23), 233110. (doi:10.1063/1.4985013)

Adamu-Lema, F., Duan, M. , Berrada, S., Lee, J., Al-Ameri, T. , Georgiev, V. and Asenov, A. (2017) Modelling and simulation of advanced semiconductor devices. ECS Transactions, 80(4), pp. 33-42. (doi:10.1149/08004.0033ecst)

Seo, J., Lee, J. and Shin, M. (2014) Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications. IEEE Transactions on Electron Devices, 64(4), pp. 1793-1798. (doi:10.1109/TED.2017.2658673)

Conference or Workshop Item

Berrada, S., Lee, J., Georgiev, V. and Asenov, A. (2017) Effect of the Quantum Mechanical Tunneling on the Leakage Current in Ultra-scaled Si Nanowire Transistors. 12th IEEE Nanotechnology Materials and Devices Conference (NMDC 2017), Singapore, 2-4 Oct 2017. (Accepted for Publication)

Lee, J., Sadi, T., Georgiev, V. P. , Todri-Sanial, A. and Asenov, A. (2017) A Hierarchical Model for CNT and Cu-CNT Composite Interconnects: From Density Functional Theory to Circuit-Level Simulations. International Workshop on Computational Nanotechnology, Windermere, UK, 5-9 June 2017. (Unpublished)

Conference Proceedings

Lee, J. et al. (2017) The Impact of Vacancy Defects on CNT Interconnects: From Statistical Atomistic Study to Circuit Simulations. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, pp. 157-160. (doi:10.23919/SISPAD.2017.8085288)

Lee, J. et al. (2017) Atoms-to-Circuits Simulation Investigation of CNT Interconnects for Next Generation CMOS Technology. In: SISPAD 2017: International Conference on Simulation of Semiconductor Processes and Devices, Kamakura, Japan, 7-9 Sept 2017, pp. 153-156. (doi:10.23919/SISPAD.2017.8085287)

Liang, J., Lee, J., Berrada, S., Georgiev, V. , Asenov, A., Azemard-Crestani, A. and Todri-Sanial, A. (2017) Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application. In: 12th IEEE Nanotechnology Materials and Devices Conference (NMDC 2017), Singapore, 2-4 Oct 2017, (Accepted for Publication)

Liang, J. et al. (2017) A Physics-based Investigation of Pt-salt Doped Carbon Nanotubes for Local Interconnects. In: 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 02-06 Dec 2017, 35.5.1-35.5.4. ISBN 9781538635599 (doi:10.1109/IEDM.2017.8268502)

This list was generated on Tue Aug 14 16:58:49 2018 BST.