Dr Syed Nabi

  • Research Associate (Computing Science)

telephone: 01413302074
email: Syed.Nabi@glasgow.ac.uk

Research interests

Personal Site: http://www.dcs.gla.ac.uk/~waqar

Biography:

Syed Waqar Nabi is a Research Associate at the School of Computing Science, University of Glasgow, and is also an alumnus of the University. In his role as a Research Associate, he works on the EPSRC funded project “Exploiting Parallelism through Type Transformations for Hybrid Manycore Systems”, whose principal investigator is Dr Wim Vanderbauwhede. His focus is on FPGAs as the target device, where the overall challenge that is addressed in the project is how to exploit the parallelism of a given computing platform, e.g. a multicore CPU, a graphics processor (GPU) or a Field-Programmable Gate Array (FPGA), in the best possible way, without having to change the original program. 

He is part of the Glasgow Parallelism research group (GPG) in the Glasgow Systems Section (GLASS) of the School of Computing Science.

Research Interests:

  • High Performance Computing (focus on FPGAs)

  • High-level Programming and Synthesis for FPGAs

  • Acceleration of Scientific Models (Atmospheric Sciences, Computational Biology) for Heterogeneous Platforms

Teaching

I teach "Project Research Readings in Computer Science" at the School of Computing Science in the Spring semester.

Publications

List by: Type | Date

Jump to: 2017 | 2016 | 2015 | 2014
Number of items: 7.

2017

Nabi, S. W. and Vanderbauwhede, W. (2017) Type-driven automated program transformations and cost modelling for optimising streaming programs on FPGAs. International Journal of Parallel Programming, (Accepted for Publication)

Nabi, S. W. and Vanderbauwhede, W. (2017) FPGA design space exploration for scientific HPC applications using a fast and accurate cost model based on roofline analysis. Journal of Parallel and Distributed Computing, (doi:10.1016/j.jpdc.2017.05.014) (In Press)

Hussain, M. A., Badar, R. and Nabi, S. W. (2017) Comparison of Hand-Written RTL code against High-Level Synthesis for Blowfish and Tiny Encrpytion Algorithm (TEA). In: International Conference on FPGA Reconfiguration for General-Purpose Computing, Hamburg, Germany, 9-10 May 2017, (Accepted for Publication)

2016

Nabi, S. W. and Vanderbauwhede, W. (2016) A Fast and Accurate Cost Model for FPGA Design Space Exploration in HPC Applications. In: 30th IEEE International Parallel & Distributed Processing Symposium, Chicago, IL, USA, 23-27 May 2016, (doi:10.1109/IPDPSW.2016.155)

Nabi, S. W. and Vanderbauwhede, W. (2016) Using Type Transformations to Generate Program Variants for FPGA Design Space Exploration. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexico City, Mexico, 7-9 Dec 2015, pp. 1-6. ISBN 9781467394055 (doi:10.1109/ReConFig.2015.7393365)

2015

Nabi, S. W. and Vanderbauwhede, W. (2015) An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs. In: HEART2015: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Boston, MA, USA, 1-2 Jun 2015,

2014

Nabi, S. W. , Hameed, S. N. and Vanderbauwhede, W. (2014) A Reconfigurable Vector Instruction Processor for Accelerating a Convection Parametrization Model on FPGAs. In: HEART2014: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Sendai, Japan, 9-11 Jun 2014,

This list was generated on Sat Oct 21 01:44:29 2017 BST.
Number of items: 7.

Articles

Nabi, S. W. and Vanderbauwhede, W. (2017) Type-driven automated program transformations and cost modelling for optimising streaming programs on FPGAs. International Journal of Parallel Programming, (Accepted for Publication)

Nabi, S. W. and Vanderbauwhede, W. (2017) FPGA design space exploration for scientific HPC applications using a fast and accurate cost model based on roofline analysis. Journal of Parallel and Distributed Computing, (doi:10.1016/j.jpdc.2017.05.014) (In Press)

Conference Proceedings

Hussain, M. A., Badar, R. and Nabi, S. W. (2017) Comparison of Hand-Written RTL code against High-Level Synthesis for Blowfish and Tiny Encrpytion Algorithm (TEA). In: International Conference on FPGA Reconfiguration for General-Purpose Computing, Hamburg, Germany, 9-10 May 2017, (Accepted for Publication)

Nabi, S. W. and Vanderbauwhede, W. (2016) A Fast and Accurate Cost Model for FPGA Design Space Exploration in HPC Applications. In: 30th IEEE International Parallel & Distributed Processing Symposium, Chicago, IL, USA, 23-27 May 2016, (doi:10.1109/IPDPSW.2016.155)

Nabi, S. W. and Vanderbauwhede, W. (2016) Using Type Transformations to Generate Program Variants for FPGA Design Space Exploration. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexico City, Mexico, 7-9 Dec 2015, pp. 1-6. ISBN 9781467394055 (doi:10.1109/ReConFig.2015.7393365)

Nabi, S. W. and Vanderbauwhede, W. (2015) An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs. In: HEART2015: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Boston, MA, USA, 1-2 Jun 2015,

Nabi, S. W. , Hameed, S. N. and Vanderbauwhede, W. (2014) A Reconfigurable Vector Instruction Processor for Accelerating a Convection Parametrization Model on FPGAs. In: HEART2014: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Sendai, Japan, 9-11 Jun 2014,

This list was generated on Sat Oct 21 01:44:29 2017 BST.