Dr Haiping Zhou

  • Research Technologist (Electronic and Nanoscale Engineering)

telephone: 01413303236
email: Haiping.Zhou@glasgow.ac.uk

Research interests

Biography

Haiping Zhou received her BSc and MEng degrees in Semiconductor Physics and Devices from Jilin University and Tsinghua University, and PhD from the University of Glasgow. She is the Research Technologist leading the research work in the laboratory of plasma processing science and technology in the James Watt Nanofabrication Centre (JWNC), the University of Glasgow.

Research Interests

My main research activities are in the area of plasma processing science and technologies for micro/nanometer scale pattern transfer to generate micro/nanometer scale structures and optical/electronic/biochemical devices and systems.

I have extensive experience in micro/nano fabrication technologies in electron-beam and photolithography, micromachining for MEMS/NEMS sensors on 3-D structures with nanometer scale resolutions, process integration and evaluation, design and characterisation of semiconductor materials and devices.

Expertise

Plasma processing science and technologies, micro/nano-fabrications, process integration and evaluation, micromachining for MEMS/NEMS.

Selected publications

All publications

List by: Type | Date

Jump to: 2017 | 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2001 | 2000 | 1999 | 1998 | 1994
Number of items: 83.

2017

Zhou, H., Fu, Y.-C. and Mirza, M. (2017) Characterization of Al2O3 and HfO2 Grown on Metal Surfaces with Thermal and Plasma Enhanced Atomic Layer Deposition. AVS 17th International Conference on Atomic Layer Deposition (ALD 2017) featuring the 4th International Atomic Layer Etching Workshop (ALE 2017), Denver, CO, USA, 15-18 Jul 2017.

Wang, J., Al-Khalidi, A., Alharbi, K., Ofiare, A., Zhou, H., Wasige, E. and Figueiredo, J. (2017) High Performance Resonant Tunneling Diode Oscillators as Terahertz Sources. In: European Microwave Conference, London, 3-7 Oct 2016, pp. 341-344. ISBN 9782874870439 (doi:10.1109/EuMC.2016.7824348)

2016

Wang, J., Khalidi, A., Alharbi, K., Ofiare, A., Zhou, H. and Wasige, E. (2016) G-Band MMIC Resonant Tunneling Diode Oscillators. In: 2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS), Toyama, Japan, 26-30 Jun 2016, ISBN 9781509019649 (doi:10.1109/ICIPRM.2016.7528736)

2015

Taylor, R. J. E. et al. (2015) Coherently coupled photonic-crystal surface-emitting laser array. IEEE Journal of Selected Topics in Quantum Electronics, 21(6), 4900307. (doi:10.1109/JSTQE.2015.2417998)

Ge, Y. , Zhang, Y., Weaver, J. M.R., Zhou, H. and Dobson, P. S. (2015) Topography-free sample for thermal spatial response measurement of scanning thermal microscopy. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 33, 06FA03. (doi:10.1116/1.4933172)

Taylor, R.J.E., Childs, D.T.D., Ivanov, P., Stevens, B.J., Babazadeh, N., Crombie, A.J., Ternent, G., Thoms, S., Zhou, H. and Hogg, R.A. (2015) Electronic control of coherence in a two-dimensional array of photonic crystal surface emitting lasers. Scientific Reports, 5, 13203. (doi:10.1038/srep13203) (PMID:26289621) (PMCID:PMC4542471)

Wang, J., Alharbi, K., Ofiare, A., Zhou, H., Khalid, A., Cumming, D. and Wasige, E. (2015) High Performance Resonant Tunneling Diode Oscillators for THz Applications. In: 2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), New Orleans, LA, USA, 11-14 Oct 2015, pp. 1-4. ISBN 9781479984947 (doi:10.1109/CSICS.2015.7314509)

Zhou, H., Li, X. and Fu, Y. (2015) Low-Leakage Current and Damage-Free SiNx Deposition at 30oC By Inductively Coupled Plasma with Neutral Beams by Neutralization Grid Plate. In: 59th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN 2015), San Diego, CA, USA, 26-29 May 2015,

2014

Mirza, M. M., MacLaren, D. A., Samarelli, A., Holmes, B. M., Zhou, H., Thoms, S., MacIntyre, D. and Paul, D. J. (2014) Determining the electronic performance limitations in top-down fabricated Si nanowires with mean widths down to 4 nm. Nano Letters, 14(11), pp. 6056-6060. (doi:10.1021/nl5015298)

Brown, R., Macfarlane, D., Al-Khalidi, A., Li, X., Ternent, G., Zhou, H., Thayne, I. and Wasige, E. (2014) A sub-critical barrier thickness normally-off AlGaN/GaN MOS-HEMT. IEEE Electron Device Letters, 35(9), pp. 906-908. (doi:10.1109/LED.2014.2334394)

2013

Li, X., Ignatova, O., Cao, M., Peralagu, U. , Steer, M., Mirza, M., Zhou, H. and Thayne, I. (2013) 10 nm vertical In0.53Ga0.47As line etching process for III-V MOSFET fabrication by using inductively coupled plasma (ICP) etcher in Cl2/CH4/H2 chemistry. In: 26th International Microprocesses and Nanotechnology Conference (MNC), Royton Sapporo, Hokkaido, Japan, 5-8 Nov 2013,

2012

Mirza, M. M., Zhou, H., Velha, P., Li, X., Docherty, K. E., Samarelli, A., Ternent, G. and Paul, D. J. (2012) Nanofabrication of high aspect ratio (∼50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 30(6), 06FF02. (doi:10.1116/1.4755835)

Mirza, M. M. A., Zhou, H., Docherty, K., Thoms, S., Macintyre, D. and Paul, D. (2012) High Aspect Ratio (~25:1) Sub-10 Nm HSQ Lines Using Electron Beam Lithography. In: EIPBN 2012: The 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa,HI USA, 29 May - 01 June 2012., Waikoloa, HI, USA, 29 May - 1 June 2012,

Li, X., Zhou, H., Hill, R.J.W., Holland, M. and Thayne, I. (2012) A low damage etching process of sub-100 nm platinum gate line for III-V metal-oxide-semiconductor field-effect transistor fabrication and the optical emission spectrometry of the inductively coupled plasma of SF6/C4F8. Japanese Journal of Applied Physics, 51(1), (doi:10.1143/JJAP.51.01AB01)

Mirza, M.M., Velha, P., Ternent, G., Zhou, H.P., Docherty, K.E. and Paul, D.J. (2012) Silicon nanowire devices with widths below 5nm. In: 12th IEEE Conference on Nanotechnology, Birmingham, UK, 20-23 Aug 2012, (doi:10.1109/NANO.2012.6322005)

Mirza, M. M., Zhou, H., Velha, P., Li, X., Docherty, K. E., Samarelli, A., Ternent, G. and Paul, D. J. (2012) Nanofabrication of high aspect ratio (˜50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching. In: EIPBN 2012: The 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa,HI USA, 29 May - 01 June 2012,

2011

Bentley, S. et al. (2011) Electron mobility in surface- and buried- channel flatband In0.53Ga0.47As MOSFETs with ALD Al2O3 gate dielectric. IEEE Electron Device Letters, 32(4), pp. 494-496. (doi:10.1109/LED.2011.2107876)

Li, X., Zhou, H., Hill, R. J.W., Holland, M. and Thayne, I. G. (2011) A low damage etching process of sub-100 nm platinum gate line for III-V MOSFET fabrication and the optical emission spectrometry of the inductively coupled plasma of SF6/C4F8. In: ISPlasma 2011: 3rd International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials, Nagoya, Japan, 6-9 March 2011,

2010

Taking, S. et al. (2010) Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al2O3 formed by thermal oxidation of evaporated aluminium. Electronics Letters, 46(4), pp. 301-302. (doi:10.1049/el.2010.2781)

Li, X., Bentley, S., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I.G. (2010) A low damage fully self-aligned gate-last process for fabricating sub-100 nm gate length enhancement mode GaAs MOSFETs. In: 54th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication, Anchorage, USA, June 2010,

Li, X., Bentley, S., McLelland, H., Holland, M., Zhou, H., Thoms, S., Macintyre, D. and Thayne, I. (2010) Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 28(6), C6L1. (doi:10.1116/1.3501355)

Li, X., Bentley, S., McLelland, H., Holland, M., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I. (2010) Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 28(6), (doi:10.1116/1.3501355)

Li, X., Zhou, H., Hill, R.J.W., Longo, P., Holland, M. and Thayne, I.G. (2010) Dry etching device quality high-kappa GaxGdyOz gate oxide in SiCl4 chemistry for low resistance ohmic contact realisation in fabricating III-V MOSFETs. Microelectronic Engineering, 87(5-8), pp. 1587-1589. (doi:10.1016/j.mee.2009.11.011)

Taking, S., Banerjee, A., Zhou, H., Li, X., MacFarlane, D., Dabiran, A. and Wasige, E. (2010) Thin Al2O3 formed by thermal oxidation of evaporated aluminium for AlN/GaN MOS-HEMT technology. In: UKNC Conference, Cork, Ireland, 12-13 Jan 2010,

2009

Hill, R.J.W. et al. (2009) Deep sub-micron and self-aligned flatband III–V MOSFETs. In: Device Research Conference, 2009 (DRC 2009), University Park, PA, USA, 22-24 Jun 2009, pp. 251-252. (doi:10.1109/DRC.2009.5354900)

Krasa, D., Wilkinson, C.D.W., Gadegaard, N., Kong, X., Zhou, H., Roberts, A.P., Muxworthy, A.R. and Williams, W. (2009) Nanofabrication of two-dimensional arrays of magnetite particles for fundamental rock magnetic studies. Journal of Geophysical Research: Solid Earth, 114, B02104. (doi:10.1029/2008JB006017)

Freescale Semiconductor, Inc. (2009) III-V MOSFET Fabrication and Device (Fabrication process of e.g. group III-V MOSFET for nano complementary metal oxide semiconductor application, involves heat treating metal contact structure to produce alloy region within semiconductor substrate). .

Li, X., Hill, R.J.W., Longo, P., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I.G. (2009) 100 nm gate length enhancement mode GaAs MOSFETs fabricated by a fully self-aligned process. In: UK Compound Semiconductor Conference 2009, Sheffield, UK, 1-2 July 2009,

Li, X., Hill, R.J.W., Longo, P., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I.G. (2009) Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs MOSFETs. In: EIPBN 2009: The 53rd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Marco Island, Florida, USA, 24-29 May 2009,

Li, X., Hill, R.J.W., Longo, P., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I.G. (2009) Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 27(6), pp. 3153-3157. (doi:10.1116/1.3256624)

Thayne, I.G. et al. (2009) Review of current status of III-V MOSFETs. ECS Transactions, 19(5), pp. 275-286. (doi:10.1149/1.3119552)

Thayne, I., Li, X., Jansen, W., Ignatova, O., Bentley, S., Zhou, H., Macintyre, D., Thoms, S. and Hill, R. (2009) Development of III-V MOSFET process modules compatible with silicon ULSI manufacture. ECS Transactions, 25(7), pp. 385-395. (doi:10.1149/1.3203975)

2008

Li, X., Zhou, H., Hill, R., Holland, M. and Thayne, I.G. (2008) Low damage inductively coupled plasma etching of sub-100 nm platinum gate line in SF6/C4F8 for III-V MOSFET fabrication process. In: 34th International Conference on Micro- and Nano-Engineering (MNE 2008), Athens, Greece, 15-18 September 2008,

Kong, X., Krasa, D., Zhou, H. P., Williams, W., McVitie, S., Weaver, J. M. R. and Wilkinson, C. D. W. (2008) Very high resolution etching of magnetic nanostructures in organic gases. Microelectronic Engineering, 85(5-6), pp. 988-991. (doi:10.1016/j.mee.2007.12.006)

Hill, R.J.W. et al. (2008) 1 μm gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737μS/μm. Electronics Letters, 44, pp. 498-500. (doi:10.1049/el:20080470)

Hill, R.J.W., Moran, D.A.J., Li, X., Zhou, H., Macintyre, D.S., Thoms, S., Asenov, A. and Thayne, I.G. (2008) Ino.75Gao.25As channel III–V MOSFETs with leading performance metrics. In: Proceedings of the IEEE Silicon Nanoelectronics Workshop, 15-16 June 2008, Honolulu, Hawaii. IEEE Computer Society: Piscataway, N.J., USA. ISBN 9781424420711 (doi:10.1109/SNW.2008.5418447)

Kalna, K. et al. (2008) III-V MOSFETs for digital applications with silicon co-integration. In: 7th International Conference on Advanced Semiconductor Devices and Microsystems, Smolenice, Slovakia, 12-16 October 2008, pp. 39-46. ISBN 9781424423255 (doi:10.1109/ASDAM.2008.4743354)

Li, X., Hill, R.J.W., Zhou, H. P., Wilkinson, C.D.W. and Thayne, I.G. (2008) A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs. Microelectronic Engineering, 85(5-6), pp. 996-999. (doi:10.1016/j.mee.2007.12.064)

Li, X., Zhou, H.P., Abrokwah, J., Zurcher, P., Rajagopalan, K., Liu, W., Gregory, R., Passlack, M. and Thayne, I.G. (2008) Low damage ashing and etching processes for ion implanted resist and Si3N4 removal by ICP and RIE methods. Microelectronic Engineering, 85(5-6), pp. 966-968. (doi:10.1016/j.mee.2007.12.056)

2007

Hill, R.J.W. et al. (2007) Enhancement-mode GaAs MOSFETs with an In0.3 Ga0.7As channel, a mobility of over 5000 cm2/V ·s, and transconductance of over 475 μS/μm. IEEE Electron Device Letters, 28(12), pp. 1080-1082. (doi:10.1109/LED.2007.910009)

Li, X., Zhou, H., Hill, R.J.W., Wilkinson, C.D.W. and Thayne, I.G. (2007) Dry etching of a device quality high-k GaxGdyOz gate oxide in CH4/H2–O2 chemistry for the fabrication of III–V MOSFETs. Microelectronic Engineering, 84(5-8), pp. 1124-1127. (doi:10.1016/j.mee.2007.01.045)

Hill, R.J.W., Moran, D.A.J., Li, X., Zhou, H., Macintyre, D., Thoms, S., Droopad, R., Passlack, M. and Thayne, I.G. (2007) 180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm. Electronics Letters, 43, pp. 543-545. (doi:10.1049/el:20070427)

Passlack, M. et al. (2007) High mobility III-V MOSFETs for RF and digital applications. In: IEEE International Electron Devices Meeting (IEDM 2007), Washington DC, USA, 10-12 December 2007, pp. 621-624. ISBN 9781424415083 (doi:10.1109/IEDM.2007.4419016)

Hill, R. J. W., Holland, M., Li, X., Macintyre, D., Moran, D., Stanley, C. R., Thoms, S., Zhou, H. and Thayne, I. G. (2007) Recent Developments in III-V MOSFETs Technology. In: 15th International Symposium Nanostructures: Physics and Technology, Novosibirsk, Russia, 25-29 June 2007, pp. 134-136. ISBN 9785936340222

Moran, D. A. J. et al. (2007) III-V Enhancement Mode MOSFETs for Digital Applications. In: IBM MRC Oxide Workshop, Zurich, Switzerland, 25-27 June 2007,

Moran, D. A. J. et al. (2007) High Performance Enhancement-Mode III-V MOSFETs. In: UK Compound Semiconductor Conference 2007, Sheffield, UK, 2007,

Moran, D.A.J. et al. (2007) High Performance Enhancement Mode III-V MOSFETs. IBM Workshop on Advanced Oxides, Zurich, Switzerland, June 2007.

Moran, D.A.J. et al. (2007) Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs. In: 37th European Solid State Device Research Conference (ESSDERC 2007), Munich, Germany, 11-13 September 2007, pp. 466-469. ISBN 9781424411245 (doi:10.1109/ESSDERC.2007.4430979)

Passlack, M. et al. (2007) High Mobility III-V MOSFET Technology. In: 7th Topical Workshop on Heterostructure Microelectronics (TWHM 2007), Chiba, Japan, 21-24 Aug 2007,

Passlack, M. et al. (2007) High mobility III-V MOSFET Technology. In: CS MANTECH Conference, Austin, TX, USA, 14-17 May 2007,

Rajagopalan, K. et al. (2007) Enhancement Mode n-MOSFET with High-κ Dielectric on GaAs Substrate. In: IEEE 65th Annual Device Research Conference, South Bend, Indiana, USA, 18-20 June 2007, pp. 205-206. ISBN 9781424411023 (doi:10.1109/DRC.2007.4373719)

Thayne, I. G. et al. (2007) High Performance Enhancement Mode III-V MOSFETs for Silicon Co-Integration. In: Silicon Nanoelectronics Workshop, Kyoto, Japan, 10-11 June 2007,

Thayne, I.G. et al. (2007) Recent Progress in III-V MOSFETs. In: UK Condensed Matter and Material Physics Conference, Leicester, UK, April 2007,

2006

Li, X., Zhou, H., Wilkinson, C. D.W. and Thayne, I. G. (2006) Optical emission spectrometry of plasma in low-damage sub-100 nm tungsten gate reactive ion etching process for compound semiconductor transistors. Japanese Journal of Applied Physics, 45(Pt.1), pp. 8364-8369. (doi:10.1143/JJAP.45.8364)

Li, X., Cao, X., Zhou, H., Wilkinson, C.D.W., Thoms, S., Macintyre, D., Holland, M. and Thayne, I. (2006) 30 nm Tungsten gates etched by a low damage ICP etching for the fabrication of compound semiconductor transistors. Microelectronic Engineering, 83, pp. 1152-1154. (doi:10.1016/j.mee.2006.01.073)

Li, X., Cao, X., Zhou, H., Wilkinson, C.D.W., Thoms, S., Macintyre, D.S., Holland, M.C. and Thayne, I.G. (2006) 30 nm tungsten gates etched by a low damage ICP etching for the fabrication of compound semiconductor transistors. Microelectronic Engineering, 83(4-9), pp. 1152-1154. (doi:10.1016/j.mee.2006.01.073)

Hill, R.J.W., Li, X., Moran, D.A.J., Zhou, H. and Thayne, I.G. (2006) A Low Damage Subtractive Ohmic Contact Process for III-V Mosfets. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Li, X., Zhou, H., Hill, R., Wilkinson, C. and Thayne, I. (2006) Dry etching of a device quality high-k GaxGdyOz oxide in CH4/H2-O2 chemistry for the fabrication of III-V MOSFETs. In: 32nd International Conference on Micro-and Nano-Engineering 2006, Barcelona, Spain,

Li, X., Cao, X., Zhou, H., Wilkinson, C.D.W., Thoms, S., Macintyre, D., Holland, M. and Thayne, I.G. (2006) A low damage RIE process for the fabrication of compound semiconductor based transistors with sub-100 nm tungsten gates. Microelectronic Engineering, 83(4-9), pp. 1159-1162. (doi:10.1016/j.mee.2006.01.074)

Li, X., Hill, R., Zhou, H., Wilkinson, C.D.W., Holland, M. and Thayne, I.G. (2006) GaxGdyOz Dry Etching Processes for the Fabrication of III-V MOSFET. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Li, X., Hill, R., Zhou, H., Wilkinson, C.D.W. and Thayne, I.G. (2006) A low damage RIE SiN sidewall spacer process for self-aligned sub-100nm III-V MOSFETs. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Li, X., Zhou, H., Cao, X., Wilkinson, C.D.W. and Thayne, I.G. (2006) Low damage dry etching processes for the fabrication of compound semiconductor based transistors with sub-100nm tungsten gates. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Li, X., Zhou, H., Wilkinson, C. D.W. and Thayne, I. G. (2006) Optical Emission Spectrometry of Plasma in Low-Damage Sub-100 Nm Tungsten Gate Reactive Ion Etching Process for Compound Semiconductor Transistors. 6th International Conference on Reactive Plasmas and 23rd Symposium on Plasma Processing (ICRP-6/SPP-23), 24-27 Jan 2006. pp. 8364-8369.

Thayne, I.G. et al. (2006) III-V MOSFETs for Digital Applications: An Overview. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Zhou, H., Elgaid, K., Wilkinson, C. and Thayne, I. (2006) Low-hydrogen-content silicon nitride deposited at room temperature by inductively coupled plasma deposition. Japanese Journal of Applied Physics, 45(Pt.1), pp. 8388-8392. (doi:10.1143/JJAP.45.8388)

2005

Cao, X. et al. (2005) Low damage sputter deposition of tungsten for decanano compound semiconductor transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 23(6), pp. 3138-3142. (doi:10.1116/1.2127937)

Elgaid, K., Zhou, H., Wilkinson, C. and Thayne, I. (2005) Room temperature deposited Si3N4 characterization and applications in MMICs. In: 8th International symposium on Silicon Nitride and Silicon dioxide thin insulating films and emerging dielectrics, Quebec, Canada,

Li, X., Cao, X., Zhou, H., Wilkinson, C., Thoms, S., Macintyre, D., Holland, M. and Thayne, I. (2005) A low damage RIE process for the fabrication of cmpound semiconductor based transistors wtih sub-100nm tungsten gates. In: 31st International Conference on Micro and Nano-Engineering 2005, Vienna, Austria,

Zhou, H., Sim, C., Glidle, A., Hodson, C., Kinsey, R. and Wilkinson, C.D.W. (2005) Plasma deposition of thin films. In: D'Agostino, R. (ed.) Plasma Processes and Polymers. WILEY-VCH: Weinheim, pp. 77-86. ISBN 9783527404872

2004

Elgaid, K., Zhou, H., Wilkinson, C.D.W. and Thayne, I.G. (2004) Low temperature high density Si3N4 MIM capacitor technology for MMMIC and RF-MEMs applications. Microelectronic Engineering, 73-4, pp. 452-455. (doi:10.1016/j.mee.2004.03.016)

Boyd, E., Zhou, H., McLelland, H., Moran, D.A.J., Thoms, S. and Thayne, I.G. (2004) Fabrication of 30nm T-gate high electron mobility transistors using a bi-Layer of PMMA and UVIII. In: 2004 IEEE Conference on Optoelectronic and Microelectronic Materials and Devices, Brisbane, Australia, 8-10 December 2004, pp. 25-28. ISBN 0780388208 (doi:10.1109/COMMAD.2004.1577483)

Elgaid, K., McLelland, H., Cao, X., Boyd, E., Moran, D., Thoms, S., Zhou, H., Wilkinson, C., Stanley, C. and Thayne, I. (2004) An array-based design methodology for the realisation of 94GHz MMMIC amplifiers. In: European Gallium Arsenide and other Compound Semiconductors Application Symposium,GaAs 2004, Amsterdam, The Netherlands,

Elgaid, K., Zhou, H., Wilkinson, C. and Thayne, I. (2004) Low temperature high density highly uniform Si3N4 technology for passive and active devices in MMMIC applications. In: GaAs Mantech 2004, Tampa, USA,

2003

Elgaid, K., Zhou, H., Wilkinson, C. and Thayne, I. (2003) Low temperature high density Si3N4 MIM capacitors technology for MMIC and RF-MEMs applications. In: Microelectronic and Nanoelectronic Engineering, Cambridge, UK,

Zhou, H., Sim, C., Hodson, C., Kinsey, R. and Wilkinson, C. (2003) Deposition of ammonia-free silicon nitride using inductively coupled plasma at low temperature. In: 16th International Symposium on Plasma Chemistry, Sicily, Italy,

2001

Chong, B.K., Zhou, H., Mills, G., Donaldson, L. and Weaver, J.M.R. (2001) Scanning Hall probe microscopy on an atomic force microscope tip. Journal of Vacuum Science and Technology A: Vacuum, Surfaces, and Films, 19(4), pp. 1769-1772.

2000

Zhou, H., Chong, B.K., Stopford, P., Mills, G., Midha, A., Donaldson, L. and Weaver, J. (2000) Lithographically defined nano and micro sensors using "float coating" of resist and electron beam lithography. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 18(6), pp. 3594-3599. (doi:10.1116/1.1321271)

1999

Zhou, H., Midha, A., Mills, G., Donaldson, L. and Weaver, J.M.R. (1999) Scanning near-field optical spectroscopy and imaging using nanofabricated probes. Applied Physics Letters, 75(13), pp. 1824-1826. (doi:10.1063/1.124840)

Zhou, H., Midha, A., Bruchhaus, L., Mills, G., Donaldson, L. and Weaver, J.M.R. (1999) Novel scanning near-field optical microscopy/atomic force microscope probes by combined micromachining and electron-beam nanolithography. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 17(5), p. 1954. (doi:10.1116/1.590855)

Zhou, H., Mills, G., Chong, B.K., Midha, A., Donaldson, L. and Weaver, J.M.R. (1999) Recent progress in the functionalization of atomic force microscope probes using electron-beam nanolithography. Journal of Vacuum Science and Technology A: Vacuum, Surfaces, and Films, 17(4), pp. 2233-2239. (doi:10.1116/1.581753)

1998

Mills, G., Zhou, H., Midha, A., Donaldson, L. and Weaver, J.M.R. (1998) Scanning thermal microscopy using batch fabricated thermocouple probes. Applied Physics Letters, 72(22), pp. 2900-2902. (doi:10.1063/1.121453)

Zhou, H., Midha, A., Mills, G., Thoms, S., Murad, S.K. and Weaver, J.M.R. (1998) Generic scanned-probe microscope sensors by combined micromachining and electron-beam lithography. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 16(1), pp. 54-58. (doi:10.1116/1.589835)

1994

Zhou, H. and Sotomayor Torres, C.M. (1994) Low-temperature emission of Al0.48In0.52As under high pressures. Journal of Applied Physics, 75(7), pp. 3571-3578. (doi:10.1063/1.356068)

This list was generated on Tue Jun 27 16:40:24 2017 BST.
Number of items: 83.

Articles

Taylor, R. J. E. et al. (2015) Coherently coupled photonic-crystal surface-emitting laser array. IEEE Journal of Selected Topics in Quantum Electronics, 21(6), 4900307. (doi:10.1109/JSTQE.2015.2417998)

Ge, Y. , Zhang, Y., Weaver, J. M.R., Zhou, H. and Dobson, P. S. (2015) Topography-free sample for thermal spatial response measurement of scanning thermal microscopy. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 33, 06FA03. (doi:10.1116/1.4933172)

Taylor, R.J.E., Childs, D.T.D., Ivanov, P., Stevens, B.J., Babazadeh, N., Crombie, A.J., Ternent, G., Thoms, S., Zhou, H. and Hogg, R.A. (2015) Electronic control of coherence in a two-dimensional array of photonic crystal surface emitting lasers. Scientific Reports, 5, 13203. (doi:10.1038/srep13203) (PMID:26289621) (PMCID:PMC4542471)

Mirza, M. M., MacLaren, D. A., Samarelli, A., Holmes, B. M., Zhou, H., Thoms, S., MacIntyre, D. and Paul, D. J. (2014) Determining the electronic performance limitations in top-down fabricated Si nanowires with mean widths down to 4 nm. Nano Letters, 14(11), pp. 6056-6060. (doi:10.1021/nl5015298)

Brown, R., Macfarlane, D., Al-Khalidi, A., Li, X., Ternent, G., Zhou, H., Thayne, I. and Wasige, E. (2014) A sub-critical barrier thickness normally-off AlGaN/GaN MOS-HEMT. IEEE Electron Device Letters, 35(9), pp. 906-908. (doi:10.1109/LED.2014.2334394)

Mirza, M. M., Zhou, H., Velha, P., Li, X., Docherty, K. E., Samarelli, A., Ternent, G. and Paul, D. J. (2012) Nanofabrication of high aspect ratio (∼50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 30(6), 06FF02. (doi:10.1116/1.4755835)

Li, X., Zhou, H., Hill, R.J.W., Holland, M. and Thayne, I. (2012) A low damage etching process of sub-100 nm platinum gate line for III-V metal-oxide-semiconductor field-effect transistor fabrication and the optical emission spectrometry of the inductively coupled plasma of SF6/C4F8. Japanese Journal of Applied Physics, 51(1), (doi:10.1143/JJAP.51.01AB01)

Bentley, S. et al. (2011) Electron mobility in surface- and buried- channel flatband In0.53Ga0.47As MOSFETs with ALD Al2O3 gate dielectric. IEEE Electron Device Letters, 32(4), pp. 494-496. (doi:10.1109/LED.2011.2107876)

Taking, S. et al. (2010) Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al2O3 formed by thermal oxidation of evaporated aluminium. Electronics Letters, 46(4), pp. 301-302. (doi:10.1049/el.2010.2781)

Li, X., Bentley, S., McLelland, H., Holland, M., Zhou, H., Thoms, S., Macintyre, D. and Thayne, I. (2010) Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 28(6), C6L1. (doi:10.1116/1.3501355)

Li, X., Bentley, S., McLelland, H., Holland, M., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I. (2010) Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 28(6), (doi:10.1116/1.3501355)

Li, X., Zhou, H., Hill, R.J.W., Longo, P., Holland, M. and Thayne, I.G. (2010) Dry etching device quality high-kappa GaxGdyOz gate oxide in SiCl4 chemistry for low resistance ohmic contact realisation in fabricating III-V MOSFETs. Microelectronic Engineering, 87(5-8), pp. 1587-1589. (doi:10.1016/j.mee.2009.11.011)

Krasa, D., Wilkinson, C.D.W., Gadegaard, N., Kong, X., Zhou, H., Roberts, A.P., Muxworthy, A.R. and Williams, W. (2009) Nanofabrication of two-dimensional arrays of magnetite particles for fundamental rock magnetic studies. Journal of Geophysical Research: Solid Earth, 114, B02104. (doi:10.1029/2008JB006017)

Li, X., Hill, R.J.W., Longo, P., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I.G. (2009) Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 27(6), pp. 3153-3157. (doi:10.1116/1.3256624)

Thayne, I.G. et al. (2009) Review of current status of III-V MOSFETs. ECS Transactions, 19(5), pp. 275-286. (doi:10.1149/1.3119552)

Thayne, I., Li, X., Jansen, W., Ignatova, O., Bentley, S., Zhou, H., Macintyre, D., Thoms, S. and Hill, R. (2009) Development of III-V MOSFET process modules compatible with silicon ULSI manufacture. ECS Transactions, 25(7), pp. 385-395. (doi:10.1149/1.3203975)

Kong, X., Krasa, D., Zhou, H. P., Williams, W., McVitie, S., Weaver, J. M. R. and Wilkinson, C. D. W. (2008) Very high resolution etching of magnetic nanostructures in organic gases. Microelectronic Engineering, 85(5-6), pp. 988-991. (doi:10.1016/j.mee.2007.12.006)

Hill, R.J.W. et al. (2008) 1 μm gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737μS/μm. Electronics Letters, 44, pp. 498-500. (doi:10.1049/el:20080470)

Li, X., Hill, R.J.W., Zhou, H. P., Wilkinson, C.D.W. and Thayne, I.G. (2008) A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs. Microelectronic Engineering, 85(5-6), pp. 996-999. (doi:10.1016/j.mee.2007.12.064)

Li, X., Zhou, H.P., Abrokwah, J., Zurcher, P., Rajagopalan, K., Liu, W., Gregory, R., Passlack, M. and Thayne, I.G. (2008) Low damage ashing and etching processes for ion implanted resist and Si3N4 removal by ICP and RIE methods. Microelectronic Engineering, 85(5-6), pp. 966-968. (doi:10.1016/j.mee.2007.12.056)

Hill, R.J.W. et al. (2007) Enhancement-mode GaAs MOSFETs with an In0.3 Ga0.7As channel, a mobility of over 5000 cm2/V ·s, and transconductance of over 475 μS/μm. IEEE Electron Device Letters, 28(12), pp. 1080-1082. (doi:10.1109/LED.2007.910009)

Li, X., Zhou, H., Hill, R.J.W., Wilkinson, C.D.W. and Thayne, I.G. (2007) Dry etching of a device quality high-k GaxGdyOz gate oxide in CH4/H2–O2 chemistry for the fabrication of III–V MOSFETs. Microelectronic Engineering, 84(5-8), pp. 1124-1127. (doi:10.1016/j.mee.2007.01.045)

Hill, R.J.W., Moran, D.A.J., Li, X., Zhou, H., Macintyre, D., Thoms, S., Droopad, R., Passlack, M. and Thayne, I.G. (2007) 180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm. Electronics Letters, 43, pp. 543-545. (doi:10.1049/el:20070427)

Li, X., Zhou, H., Wilkinson, C. D.W. and Thayne, I. G. (2006) Optical emission spectrometry of plasma in low-damage sub-100 nm tungsten gate reactive ion etching process for compound semiconductor transistors. Japanese Journal of Applied Physics, 45(Pt.1), pp. 8364-8369. (doi:10.1143/JJAP.45.8364)

Li, X., Cao, X., Zhou, H., Wilkinson, C.D.W., Thoms, S., Macintyre, D., Holland, M. and Thayne, I. (2006) 30 nm Tungsten gates etched by a low damage ICP etching for the fabrication of compound semiconductor transistors. Microelectronic Engineering, 83, pp. 1152-1154. (doi:10.1016/j.mee.2006.01.073)

Li, X., Cao, X., Zhou, H., Wilkinson, C.D.W., Thoms, S., Macintyre, D.S., Holland, M.C. and Thayne, I.G. (2006) 30 nm tungsten gates etched by a low damage ICP etching for the fabrication of compound semiconductor transistors. Microelectronic Engineering, 83(4-9), pp. 1152-1154. (doi:10.1016/j.mee.2006.01.073)

Li, X., Cao, X., Zhou, H., Wilkinson, C.D.W., Thoms, S., Macintyre, D., Holland, M. and Thayne, I.G. (2006) A low damage RIE process for the fabrication of compound semiconductor based transistors with sub-100 nm tungsten gates. Microelectronic Engineering, 83(4-9), pp. 1159-1162. (doi:10.1016/j.mee.2006.01.074)

Zhou, H., Elgaid, K., Wilkinson, C. and Thayne, I. (2006) Low-hydrogen-content silicon nitride deposited at room temperature by inductively coupled plasma deposition. Japanese Journal of Applied Physics, 45(Pt.1), pp. 8388-8392. (doi:10.1143/JJAP.45.8388)

Cao, X. et al. (2005) Low damage sputter deposition of tungsten for decanano compound semiconductor transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 23(6), pp. 3138-3142. (doi:10.1116/1.2127937)

Elgaid, K., Zhou, H., Wilkinson, C.D.W. and Thayne, I.G. (2004) Low temperature high density Si3N4 MIM capacitor technology for MMMIC and RF-MEMs applications. Microelectronic Engineering, 73-4, pp. 452-455. (doi:10.1016/j.mee.2004.03.016)

Chong, B.K., Zhou, H., Mills, G., Donaldson, L. and Weaver, J.M.R. (2001) Scanning Hall probe microscopy on an atomic force microscope tip. Journal of Vacuum Science and Technology A: Vacuum, Surfaces, and Films, 19(4), pp. 1769-1772.

Zhou, H., Chong, B.K., Stopford, P., Mills, G., Midha, A., Donaldson, L. and Weaver, J. (2000) Lithographically defined nano and micro sensors using "float coating" of resist and electron beam lithography. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 18(6), pp. 3594-3599. (doi:10.1116/1.1321271)

Zhou, H., Midha, A., Mills, G., Donaldson, L. and Weaver, J.M.R. (1999) Scanning near-field optical spectroscopy and imaging using nanofabricated probes. Applied Physics Letters, 75(13), pp. 1824-1826. (doi:10.1063/1.124840)

Zhou, H., Midha, A., Bruchhaus, L., Mills, G., Donaldson, L. and Weaver, J.M.R. (1999) Novel scanning near-field optical microscopy/atomic force microscope probes by combined micromachining and electron-beam nanolithography. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 17(5), p. 1954. (doi:10.1116/1.590855)

Zhou, H., Mills, G., Chong, B.K., Midha, A., Donaldson, L. and Weaver, J.M.R. (1999) Recent progress in the functionalization of atomic force microscope probes using electron-beam nanolithography. Journal of Vacuum Science and Technology A: Vacuum, Surfaces, and Films, 17(4), pp. 2233-2239. (doi:10.1116/1.581753)

Mills, G., Zhou, H., Midha, A., Donaldson, L. and Weaver, J.M.R. (1998) Scanning thermal microscopy using batch fabricated thermocouple probes. Applied Physics Letters, 72(22), pp. 2900-2902. (doi:10.1063/1.121453)

Zhou, H., Midha, A., Mills, G., Thoms, S., Murad, S.K. and Weaver, J.M.R. (1998) Generic scanned-probe microscope sensors by combined micromachining and electron-beam lithography. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 16(1), pp. 54-58. (doi:10.1116/1.589835)

Zhou, H. and Sotomayor Torres, C.M. (1994) Low-temperature emission of Al0.48In0.52As under high pressures. Journal of Applied Physics, 75(7), pp. 3571-3578. (doi:10.1063/1.356068)

Book Sections

Hill, R.J.W., Moran, D.A.J., Li, X., Zhou, H., Macintyre, D.S., Thoms, S., Asenov, A. and Thayne, I.G. (2008) Ino.75Gao.25As channel III–V MOSFETs with leading performance metrics. In: Proceedings of the IEEE Silicon Nanoelectronics Workshop, 15-16 June 2008, Honolulu, Hawaii. IEEE Computer Society: Piscataway, N.J., USA. ISBN 9781424420711 (doi:10.1109/SNW.2008.5418447)

Zhou, H., Sim, C., Glidle, A., Hodson, C., Kinsey, R. and Wilkinson, C.D.W. (2005) Plasma deposition of thin films. In: D'Agostino, R. (ed.) Plasma Processes and Polymers. WILEY-VCH: Weinheim, pp. 77-86. ISBN 9783527404872

Conference or Workshop Item

Zhou, H., Fu, Y.-C. and Mirza, M. (2017) Characterization of Al2O3 and HfO2 Grown on Metal Surfaces with Thermal and Plasma Enhanced Atomic Layer Deposition. AVS 17th International Conference on Atomic Layer Deposition (ALD 2017) featuring the 4th International Atomic Layer Etching Workshop (ALE 2017), Denver, CO, USA, 15-18 Jul 2017.

Moran, D.A.J. et al. (2007) High Performance Enhancement Mode III-V MOSFETs. IBM Workshop on Advanced Oxides, Zurich, Switzerland, June 2007.

Li, X., Zhou, H., Wilkinson, C. D.W. and Thayne, I. G. (2006) Optical Emission Spectrometry of Plasma in Low-Damage Sub-100 Nm Tungsten Gate Reactive Ion Etching Process for Compound Semiconductor Transistors. 6th International Conference on Reactive Plasmas and 23rd Symposium on Plasma Processing (ICRP-6/SPP-23), 24-27 Jan 2006. pp. 8364-8369.

Conference Proceedings

Wang, J., Al-Khalidi, A., Alharbi, K., Ofiare, A., Zhou, H., Wasige, E. and Figueiredo, J. (2017) High Performance Resonant Tunneling Diode Oscillators as Terahertz Sources. In: European Microwave Conference, London, 3-7 Oct 2016, pp. 341-344. ISBN 9782874870439 (doi:10.1109/EuMC.2016.7824348)

Wang, J., Khalidi, A., Alharbi, K., Ofiare, A., Zhou, H. and Wasige, E. (2016) G-Band MMIC Resonant Tunneling Diode Oscillators. In: 2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS), Toyama, Japan, 26-30 Jun 2016, ISBN 9781509019649 (doi:10.1109/ICIPRM.2016.7528736)

Wang, J., Alharbi, K., Ofiare, A., Zhou, H., Khalid, A., Cumming, D. and Wasige, E. (2015) High Performance Resonant Tunneling Diode Oscillators for THz Applications. In: 2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), New Orleans, LA, USA, 11-14 Oct 2015, pp. 1-4. ISBN 9781479984947 (doi:10.1109/CSICS.2015.7314509)

Zhou, H., Li, X. and Fu, Y. (2015) Low-Leakage Current and Damage-Free SiNx Deposition at 30oC By Inductively Coupled Plasma with Neutral Beams by Neutralization Grid Plate. In: 59th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN 2015), San Diego, CA, USA, 26-29 May 2015,

Li, X., Ignatova, O., Cao, M., Peralagu, U. , Steer, M., Mirza, M., Zhou, H. and Thayne, I. (2013) 10 nm vertical In0.53Ga0.47As line etching process for III-V MOSFET fabrication by using inductively coupled plasma (ICP) etcher in Cl2/CH4/H2 chemistry. In: 26th International Microprocesses and Nanotechnology Conference (MNC), Royton Sapporo, Hokkaido, Japan, 5-8 Nov 2013,

Mirza, M. M. A., Zhou, H., Docherty, K., Thoms, S., Macintyre, D. and Paul, D. (2012) High Aspect Ratio (~25:1) Sub-10 Nm HSQ Lines Using Electron Beam Lithography. In: EIPBN 2012: The 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa,HI USA, 29 May - 01 June 2012., Waikoloa, HI, USA, 29 May - 1 June 2012,

Mirza, M.M., Velha, P., Ternent, G., Zhou, H.P., Docherty, K.E. and Paul, D.J. (2012) Silicon nanowire devices with widths below 5nm. In: 12th IEEE Conference on Nanotechnology, Birmingham, UK, 20-23 Aug 2012, (doi:10.1109/NANO.2012.6322005)

Mirza, M. M., Zhou, H., Velha, P., Li, X., Docherty, K. E., Samarelli, A., Ternent, G. and Paul, D. J. (2012) Nanofabrication of high aspect ratio (˜50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching. In: EIPBN 2012: The 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa,HI USA, 29 May - 01 June 2012,

Li, X., Zhou, H., Hill, R. J.W., Holland, M. and Thayne, I. G. (2011) A low damage etching process of sub-100 nm platinum gate line for III-V MOSFET fabrication and the optical emission spectrometry of the inductively coupled plasma of SF6/C4F8. In: ISPlasma 2011: 3rd International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials, Nagoya, Japan, 6-9 March 2011,

Li, X., Bentley, S., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I.G. (2010) A low damage fully self-aligned gate-last process for fabricating sub-100 nm gate length enhancement mode GaAs MOSFETs. In: 54th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication, Anchorage, USA, June 2010,

Taking, S., Banerjee, A., Zhou, H., Li, X., MacFarlane, D., Dabiran, A. and Wasige, E. (2010) Thin Al2O3 formed by thermal oxidation of evaporated aluminium for AlN/GaN MOS-HEMT technology. In: UKNC Conference, Cork, Ireland, 12-13 Jan 2010,

Hill, R.J.W. et al. (2009) Deep sub-micron and self-aligned flatband III–V MOSFETs. In: Device Research Conference, 2009 (DRC 2009), University Park, PA, USA, 22-24 Jun 2009, pp. 251-252. (doi:10.1109/DRC.2009.5354900)

Li, X., Hill, R.J.W., Longo, P., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I.G. (2009) 100 nm gate length enhancement mode GaAs MOSFETs fabricated by a fully self-aligned process. In: UK Compound Semiconductor Conference 2009, Sheffield, UK, 1-2 July 2009,

Li, X., Hill, R.J.W., Longo, P., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S. and Thayne, I.G. (2009) Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs MOSFETs. In: EIPBN 2009: The 53rd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Marco Island, Florida, USA, 24-29 May 2009,

Li, X., Zhou, H., Hill, R., Holland, M. and Thayne, I.G. (2008) Low damage inductively coupled plasma etching of sub-100 nm platinum gate line in SF6/C4F8 for III-V MOSFET fabrication process. In: 34th International Conference on Micro- and Nano-Engineering (MNE 2008), Athens, Greece, 15-18 September 2008,

Kalna, K. et al. (2008) III-V MOSFETs for digital applications with silicon co-integration. In: 7th International Conference on Advanced Semiconductor Devices and Microsystems, Smolenice, Slovakia, 12-16 October 2008, pp. 39-46. ISBN 9781424423255 (doi:10.1109/ASDAM.2008.4743354)

Passlack, M. et al. (2007) High mobility III-V MOSFETs for RF and digital applications. In: IEEE International Electron Devices Meeting (IEDM 2007), Washington DC, USA, 10-12 December 2007, pp. 621-624. ISBN 9781424415083 (doi:10.1109/IEDM.2007.4419016)

Hill, R. J. W., Holland, M., Li, X., Macintyre, D., Moran, D., Stanley, C. R., Thoms, S., Zhou, H. and Thayne, I. G. (2007) Recent Developments in III-V MOSFETs Technology. In: 15th International Symposium Nanostructures: Physics and Technology, Novosibirsk, Russia, 25-29 June 2007, pp. 134-136. ISBN 9785936340222

Moran, D. A. J. et al. (2007) III-V Enhancement Mode MOSFETs for Digital Applications. In: IBM MRC Oxide Workshop, Zurich, Switzerland, 25-27 June 2007,

Moran, D. A. J. et al. (2007) High Performance Enhancement-Mode III-V MOSFETs. In: UK Compound Semiconductor Conference 2007, Sheffield, UK, 2007,

Moran, D.A.J. et al. (2007) Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs. In: 37th European Solid State Device Research Conference (ESSDERC 2007), Munich, Germany, 11-13 September 2007, pp. 466-469. ISBN 9781424411245 (doi:10.1109/ESSDERC.2007.4430979)

Passlack, M. et al. (2007) High Mobility III-V MOSFET Technology. In: 7th Topical Workshop on Heterostructure Microelectronics (TWHM 2007), Chiba, Japan, 21-24 Aug 2007,

Passlack, M. et al. (2007) High mobility III-V MOSFET Technology. In: CS MANTECH Conference, Austin, TX, USA, 14-17 May 2007,

Rajagopalan, K. et al. (2007) Enhancement Mode n-MOSFET with High-κ Dielectric on GaAs Substrate. In: IEEE 65th Annual Device Research Conference, South Bend, Indiana, USA, 18-20 June 2007, pp. 205-206. ISBN 9781424411023 (doi:10.1109/DRC.2007.4373719)

Thayne, I. G. et al. (2007) High Performance Enhancement Mode III-V MOSFETs for Silicon Co-Integration. In: Silicon Nanoelectronics Workshop, Kyoto, Japan, 10-11 June 2007,

Thayne, I.G. et al. (2007) Recent Progress in III-V MOSFETs. In: UK Condensed Matter and Material Physics Conference, Leicester, UK, April 2007,

Hill, R.J.W., Li, X., Moran, D.A.J., Zhou, H. and Thayne, I.G. (2006) A Low Damage Subtractive Ohmic Contact Process for III-V Mosfets. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Li, X., Zhou, H., Hill, R., Wilkinson, C. and Thayne, I. (2006) Dry etching of a device quality high-k GaxGdyOz oxide in CH4/H2-O2 chemistry for the fabrication of III-V MOSFETs. In: 32nd International Conference on Micro-and Nano-Engineering 2006, Barcelona, Spain,

Li, X., Hill, R., Zhou, H., Wilkinson, C.D.W., Holland, M. and Thayne, I.G. (2006) GaxGdyOz Dry Etching Processes for the Fabrication of III-V MOSFET. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Li, X., Hill, R., Zhou, H., Wilkinson, C.D.W. and Thayne, I.G. (2006) A low damage RIE SiN sidewall spacer process for self-aligned sub-100nm III-V MOSFETs. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Li, X., Zhou, H., Cao, X., Wilkinson, C.D.W. and Thayne, I.G. (2006) Low damage dry etching processes for the fabrication of compound semiconductor based transistors with sub-100nm tungsten gates. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Thayne, I.G. et al. (2006) III-V MOSFETs for Digital Applications: An Overview. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Elgaid, K., Zhou, H., Wilkinson, C. and Thayne, I. (2005) Room temperature deposited Si3N4 characterization and applications in MMICs. In: 8th International symposium on Silicon Nitride and Silicon dioxide thin insulating films and emerging dielectrics, Quebec, Canada,

Li, X., Cao, X., Zhou, H., Wilkinson, C., Thoms, S., Macintyre, D., Holland, M. and Thayne, I. (2005) A low damage RIE process for the fabrication of cmpound semiconductor based transistors wtih sub-100nm tungsten gates. In: 31st International Conference on Micro and Nano-Engineering 2005, Vienna, Austria,

Boyd, E., Zhou, H., McLelland, H., Moran, D.A.J., Thoms, S. and Thayne, I.G. (2004) Fabrication of 30nm T-gate high electron mobility transistors using a bi-Layer of PMMA and UVIII. In: 2004 IEEE Conference on Optoelectronic and Microelectronic Materials and Devices, Brisbane, Australia, 8-10 December 2004, pp. 25-28. ISBN 0780388208 (doi:10.1109/COMMAD.2004.1577483)

Elgaid, K., McLelland, H., Cao, X., Boyd, E., Moran, D., Thoms, S., Zhou, H., Wilkinson, C., Stanley, C. and Thayne, I. (2004) An array-based design methodology for the realisation of 94GHz MMMIC amplifiers. In: European Gallium Arsenide and other Compound Semiconductors Application Symposium,GaAs 2004, Amsterdam, The Netherlands,

Elgaid, K., Zhou, H., Wilkinson, C. and Thayne, I. (2004) Low temperature high density highly uniform Si3N4 technology for passive and active devices in MMMIC applications. In: GaAs Mantech 2004, Tampa, USA,

Elgaid, K., Zhou, H., Wilkinson, C. and Thayne, I. (2003) Low temperature high density Si3N4 MIM capacitors technology for MMIC and RF-MEMs applications. In: Microelectronic and Nanoelectronic Engineering, Cambridge, UK,

Zhou, H., Sim, C., Hodson, C., Kinsey, R. and Wilkinson, C. (2003) Deposition of ammonia-free silicon nitride using inductively coupled plasma at low temperature. In: 16th International Symposium on Plasma Chemistry, Sicily, Italy,

Patents

Freescale Semiconductor, Inc. (2009) III-V MOSFET Fabrication and Device (Fabrication process of e.g. group III-V MOSFET for nano complementary metal oxide semiconductor application, involves heat treating metal contact structure to produce alloy region within semiconductor substrate). .

This list was generated on Tue Jun 27 16:40:24 2017 BST.